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I was running PCI Express reference design simulation in Modelsim. Compilation failed and an error "cannot open top_core.vo file in read mode" was displayed. I went through respective folder, but that particular file was missing. A verilog file with same name (top_core.v) is there is same location.

After going through all the document what I understood is, verilog output file is created by Quartus II when compiled. Then why it is not happening in my case. Is there any other method to make top_core.vo from top_core.v file ?

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A .vo file is a "verilog output" file. It should be generated in the $PROJECT/simulation/modelsim/ directory. It contains your top level verilog module plus annotations that specify the timing constraints for the IO pins of your actual device so that the simulator can verify the setup-and-hold times of the IO.

You can generate it from the menu Processing >> Start >> Start EDA Netlist Writer, then you can add it to your simulation.

I think you can do functional (rather than timing) simulation by simply using the original .v source file, but honestly I don't have it working yet either.

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