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RAM (8KB, requires 13 bits A0-A12)
Start: 0110 0000 0101 0000 (6050h)
End: 1000 0000 0100 1111 (804Fh)

ROM1 (8KB, requires 13 bits A0-A12)
Start: 1000 0000 0101 0000 (8050h)
End: 1010 0000 0100 1111 (A04Fh)

ROM2 (8KB, requires 13 bits A0-A12)
Start: 1010 0000 0101 0000 (A050h)
End: 1100 0000 0101 0000 (C04Fh)

Above are the address maps. Now, how to design an address decoder when all of the 16 bits are changing?

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  • \$\begingroup\$ Check that the ones that should be 0 are 0, and that the ones that should be 1 are 1. \$\endgroup\$ Commented Sep 21, 2015 at 3:28
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    \$\begingroup\$ Even better - stop using weird data boundaries. RAM 6000h to 7FFFh, ROM1 8000h to 9FFFh, ROM2 A000h to BFFFh. Then you only have to monitor A10 - A12, and a single 74LS/HC138 will do the job. \$\endgroup\$ Commented Sep 21, 2015 at 3:33
  • \$\begingroup\$ Very strange address map; why the start and end addresses are not aligned with natural decoder boundaries? Usually address decoding is designed starting with MSB bits and decoding the minimal number of bits required for unambiguous chip select. Shadow addresses should be tolerated to minimize decoder logic; but if it must be done exactly as specified here (with no shadow) that would require very large decoder and very wide OR-gate. Suggest clarify or re-evaluate the address map requirement. Why not RAM 0x6000-0x7FFF for example, instead of 0x6050 to 0x804F? \$\endgroup\$ Commented Sep 21, 2015 at 3:33
  • \$\begingroup\$ This is the question that our university board asked us and I amn't getting the solutions anywhere at all. Only if the address had started from x000H then there wouldn't have been any confusion. \$\endgroup\$ Commented Sep 21, 2015 at 3:50

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The completely general way to decode an address map is to use a bunch of comparators, one for each boundary in the address map. These comparators need to be the full width of the address bus. The "A" input is tied to the address bus and the "B" input is set to a constant representing the start of one of the memory regions. The output is high when A < B.

In your case, the first comparator would have the value 0x6050, and its output C1 will be high for all addresses prior to the start of RAM.

The second comparator would have the value 0x8050, and its output C2 will be high for all addresses prior to the start of ROM1. The chip select for the RAM is therefore !C1 && C2.

The third comparator would have the value 0xA050, and its output C3 will be high for all addresses prior to the start of ROM2. The chip select for ROM1 is therefore !C2 && C3.

And so forth and so on.

The reason we normally select "natural" boundaries for memory segments based on their size is that this general decoding scheme reduces to a very small number of gates, once you take into account all of the constant values and "don't cares".

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  • \$\begingroup\$ You might explicitly note that the comparators are arithmetic comparators with A>B, A=B, and A<B outputs, rather than equality comparators, which are a number of exclusive-OR gates connected to an AND gate. \$\endgroup\$ Commented Sep 21, 2015 at 13:01
  • \$\begingroup\$ @WhatRoughBeast: Which part of "The output is high when A < B" confused you? \$\endgroup\$ Commented Sep 21, 2015 at 13:18
  • \$\begingroup\$ No part confused me, but I'm concerned for the questioner, who seems pretty lost. That's why I suggested you make it explicit. \$\endgroup\$ Commented Sep 21, 2015 at 13:31

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