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I am working on a block design to compute the coordinate in the complex set represented by a pixel. Given an x and y pixel value, the step size, and starting x and starting y I need to compute a coordinate in the complex plane. For instance x' = start_x + step * x

Since x is an integer I first pass it though a floating point conversion module and then through a floating point fused multiply add. This has a total latency of 24 cycles. The problem is that I also need to provide a memory address at the beginning and get it out 24 cycles later before I pass it on the the module which gets x' y' and the address. I am looking for an IP which can help with this. The closest thing I have found is a shift register but I would need 24 of them. I was thinking of maybe using a FIFO. Is there anything that just acts as a latency delay for data while other calculations are being performed?

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PS: Not sure why I called my Fused-Mul-Add fmax

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  • \$\begingroup\$ What is the throughput of the floating point conversion and fused multiply add? If it's 1 calculation per cycle, then you probably need a shift register to delay the address. If it's less (like one per 24 cycles) then you probably just need to store the address in a register, and code your floating point operations with a "done" flag to signal when the address should be retrieved (and maybe the next address shifted in?) \$\endgroup\$ Commented Jan 9, 2016 at 4:16
  • \$\begingroup\$ It is 1 per cycle. \$\endgroup\$ Commented Jan 9, 2016 at 4:16
  • \$\begingroup\$ I am doing it this way since I want to pass the data to my Mandelbrot computation module which is pipelined and I need this to feed it fast enough. \$\endgroup\$ Commented Jan 9, 2016 at 4:17
  • \$\begingroup\$ Then it sounds like you need a shift register. Maybe there is a resource-efficient way to implement it in a BRAM or something, though. \$\endgroup\$ Commented Jan 9, 2016 at 4:18
  • \$\begingroup\$ (Or look into the trick of using LUT RAM itself as shift registers. IIRC you can get a 32-bit serial shift register in a single LUT. \$\endgroup\$ Commented Jan 9, 2016 at 4:19

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Just write one. It's only a few lines of VHDL. Depth can be a generic natural, and it can take its width from the ports. Synth it independently and check that ISE/Vivado use the expected shift register mode in LUTs.

If you can't easily wrap it as a block, that calls the usefulness of the whole block diagram approach into question. Most of these things go right back to Mentor Graphics "Renoir" tool, in which wrapping VHDL as a block was easy.

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It sounds like you need a shift register.

Luckily, shift registers can be implemented fairly efficiently in Xilinx FPGAs.

From the Kintex-7 documentation.

A SLICEM function generator can also be configured as a 32-bit shift register without using the flip-flops available in a slice. Used in this way, each LUT can delay serial data from 1 to 32 clock cycles

So a 24-cycle delay for a 24-bit address could be implemented in just 6 CLB's (because there are 4 LUTs in each SLICEM CLB). Spartan devices should also have similar capabilities.

In older families, SRL was the macro used to instantiate this functionality. I'm not sure if that's still true for the current (Artix/Kintex/Virtex-7 or Spartan-6 generation) products.

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  • \$\begingroup\$ The issue is that as far as I can tell the axi stream shift registers only dely 1 cycle. I could add 24 of them but this is a pain. Is there anyway to have a shift register with a delay of 24? \$\endgroup\$ Commented Jan 9, 2016 at 4:55
  • \$\begingroup\$ I have no idea what axi stream is or how it relates to Xilinx devices or Xilinx IP, so I can't help you with that. \$\endgroup\$ Commented Jan 9, 2016 at 4:56
  • \$\begingroup\$ It looks like I can just use the ram based shift register for my purposes so thanks. \$\endgroup\$ Commented Jan 9, 2016 at 4:58
  • \$\begingroup\$ AXI Stream is an interface from ARM. It has FIFO like control signals. \$\endgroup\$ Commented Jan 9, 2016 at 8:42
  • \$\begingroup\$ @Paebbels, in that case, I'm not clear why OP can only use Axi-Stream shift registers in his/her design. \$\endgroup\$ Commented Jan 9, 2016 at 16:45

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