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I am trying to implement one of the ciphers in VHDL.

I have 2 entities: Main and block_cipher

The Main entity also have a parameter named mode which is of type : std_logic

So from main entity I want to call block_cipher on the basis of the mode value.

e.g.

blk_cipher_prc : process(mode) begin if(mode = 0) then block_cipher_0 : block_cipher port map (text, key,output); end if; end process;

But it gives me an error: ERROR:HDLCompiler:806 Syntax error near "port".

My only motive is to call the other entity on the basis of the mode value, If someone can help with my code or can provide some alternative way to do it.

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    \$\begingroup\$ Oh dear. Processes and instantiated entities or components run in parallel. Code within a process is sequential. You cannot embed parallel elements (components or other processes) in a sequential region, i.e. in a process. This is a most basic aspect of VHDL. I would recommend learning some of the basics before proceeding further. \$\endgroup\$ Commented Jul 1, 2016 at 21:47
  • \$\begingroup\$ Ok, so can I achieve the same thing without using a process \$\endgroup\$ Commented Jul 1, 2016 at 22:54
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    \$\begingroup\$ You don't 'call' hardware, hardware is there or isn't there. You instantiate a component and send signals to it. \$\endgroup\$ Commented Jul 2, 2016 at 5:02
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    \$\begingroup\$ Learn the basics of hardware design. When you can visualise the hardware you are trying to achieve (you can't "call" components out of thin air, they have to be already there at runtime, but you can use or ignore their outputs any time you want) THEN you'll be able to express it in VHDL. \$\endgroup\$ Commented Jul 2, 2016 at 13:07

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Forgive any wrong interpretations but your terminology (code, call) suggests you may see VHDL as a 'program'. It is instead a descriptor language for describing a digital electronic circuit. Recognising that distinction is paramount and you'll get confused if you don't see it clearly and unambiguously. Try to see VHDL as what it is at its heart: a glorified circuit diagram. Avoid mental comparisons with software and computer programs, which are very different.

Describing VHDL further for what you need is beyond this post. But your source file should instantiate ('connect up the wires of') your component outside of any process within your architecture.

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  • \$\begingroup\$ VHDL is also a computer language, with programs that, when executed / synthesised / compiled generate hardware. It is not just circuit diagrams, it is a language which can automatically and from algorithms generate circuit diagrams. There are all sort of valid comparisons with software design, everything inside processes is imperative code, which can call combinatorial functions and procedures. \$\endgroup\$ Commented Jul 3, 2016 at 2:26
  • \$\begingroup\$ @TEMLIB, sorry, it's a Descriptor Language. Its not a computer language, not for controlling computers, lacks lots of stuff for that. It can't be executed, only simulated or synthesised. It's translated to gates/models, not machine code. It just makes circuits, same as a netlist. VHDL starters need a distinct view. And circuit comes first, VHDL modelling of it second - good VHDL design never loses sight of that. Piles of bad VHDL about that does, implying circuits that can't be built properly. Lots of structure taken from software (it's Ada). But please send a VHDL newcomer up a clear path :-) \$\endgroup\$ Commented Jul 5, 2016 at 7:33

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