Have a few problems with my assignment.
Ive derived a truth table and come up with this :
Can someone verify if the above is correct?
Ive then got these 2 logic expressions :
Y = A'D' + C'D' + B'D'
Z = D+ B
What I want to know is (if the above is correct) Is it possible to implement the above circuit using fewer logic gates?
You have a major mistake. Look carefully at U1A. It's a NAND gate. Go back and look up what a NAND gate does.
You seem to have the function of the other two gates right.
Is it possible to implement the above circuit using fewer logic gates?
You have three different outputs, N, Y, and Z. This means that you need at least three output gates to implement the functions. So no, you can't reduce the number of gates. However, a 3-input AND gate can be made out of 2-input logic NAND gates (or equivalently NOR gates) followed by a 2-input AND gate like below:
simulate this circuit – Schematic created using CircuitLab
The function Y is simply \$ Y=\overline{ABC + D}\$. Using De-Morgan's laws we can re-write Y as \$ Y=\overline{ABC}.\overline{D}\$. Another form of writing Y can be this.
$$ \overline{Y}=ABC+D= \overline{\overline{A}+ \overline{B}+ \overline{C}}+\overline{\overline{D}}$$ Take \$ \alpha=\overline{A}+ \overline{B}+ \overline{C}\$ and \$ \beta=\overline{D}\$. Again using De-Morgan's laws we get
$$ \overline{Y}=\overline{\alpha}+\overline{\beta}=\overline{\alpha. \beta}$$ Therefore,
$$Y=\alpha.\beta$$ or $$Y=(\overline{A}+ \overline{B}+ \overline{C}).\overline{D}$$
It can also be expanded out $$Y=\overline{A}.\overline{D}+\overline{B}.\overline{D}+\overline{C}.\overline{D}$$
