I need 100MHz clock frequency to implement my HDL design on an FPGA. Is it better to use an FPGA board with 100MHz crystal oscillator or use PLL to increase the frequency? What are the advantages and disadvantages of them?
3
- \$\begingroup\$ What does the FPGA board's data sheet tell you about this? \$\endgroup\$Andy aka– Andy aka2018-03-15 13:15:13 +00:00Commented Mar 15, 2018 at 13:15
- \$\begingroup\$ I have not chosen the FPGA board yet, I would consider your advises to choose one. @Andy aka \$\endgroup\$Adhamzhon Shukurov– Adhamzhon Shukurov2018-03-15 13:18:19 +00:00Commented Mar 15, 2018 at 13:18
- \$\begingroup\$ @Andyaka Datasheet probably says that either way works. This is more of a board- or system-level question. Say, you want to clock multiple components from one clock generator, and you need to send the clock across the board. It may be more convenient to send a low frequency and use local PLLs, than to distribute a high frequency clock. \$\endgroup\$Nick Alexeev– Nick Alexeev2018-03-17 05:26:32 +00:00Commented Mar 17, 2018 at 5:26
Add a comment |
2 Answers
\$\begingroup\$ \$\endgroup\$
As long as you are able to generate the frequency you want from the available on board clock and PLL, it is better to use the PLL.
One of the main purposes of a PLL in an FPGA is to generate clocks of a desired frequency based on the available reference frequency oscillator. Using the PLL also allows you to generate different clock phases and frequencies that are guaranteed to have a fixed phase relationship, which is very useful in many designs.
In many cases, timing closure is easier with an internally generated PLL clock than a global clock input. Because of this it is not unusual to use a PLL to generate the exact same frequency as the input clock.
\$\begingroup\$ \$\endgroup\$
Generally, a PLL would be the cheaper option, as it would require a lower-frequency crystal to generate the synthesizer clock.
