Questions tagged [pll]

Question 1

I need to implement a frequency sweep covering 410-525 MHz. I’m considering several approaches but want advice on real-world practicality: Simple ramp voltage → timer IC → ??? (drive a timer or ...

Question 2

I am currently working on a redesign of one of my older PCBs. On this PCB there is a HEF4046BT used as a PLL. I needed to exchange the CPLD, which is used as a frequency divider between the ports ...

Question 3

I am looking for an IC that can generate a 50 MHz clock from a 25 MHz crystal. I know how to do this with a microcontroller with an internal PLL, but I am looking to do this with a standalone IC that ...

Question 4

Background: I am working on a project of modernizing a system for a lead acid battery charger. I will do this with a Vienna rectifier, that needs the current angle, that I get from a PLL, for control. ...

Question 5

I trying to program the ADF4001 in order to make a PLL with an N counter and R counter of 1, but I have no output on the CP pin. I am unsure if it's the way I am programming the chip or the layout I ...

Question 6

Why do we generally say that the time constant of a PLL (\$\tau\$) must be 10 to 5 times higher than the \$T_{\rm IN}\$ of our reference frequency?

Question 7

I'm modeling an Integer-N PFD/CP-based PLL in Simulink based on Example 3.2 of Rogers' book (Integrated Circuit Design for High-Speed Frequency Synthesis), but I'm not getting the same results. In the ...

Question 8

In the formula above , it is given that jitter due to flicker noise = n x timining variation / t since n/t = 1/f , shudnt the formula be timing variation / f then instead of timing variation * t (...

Question 9

https://www.ti.com/lit/an/sbaa661/sbaa661.pdf?ts=1745596081730&ref_url=https%253A%252F%252Fwww.google.com%252F This document talks about the impact of slew rate of reference source on PLL. Few ...

Question 10

I have been reading a lot about power systems lately, and am confused regarding the difference between phasor measurement units and phase locked loop? Firstly, are they different. PMU as I have read ...

Question 11

I have been trying to create a 6 MHz signal output from a 27 MHz system clock using a PLL on the Gowin 1K FPGA. As can be seen ...

Question 12

I'm working on specific multi-rate, multi-modulation modulator using a MAX 10 FPGA. The design consists of linear chain of switchable FIR filters. I faced a problem. When testing modulator on output, ...

Question 13

I'm following this tutorial on si5351, with the goal to generate variable frequency range (eventually with two clocks in quadrature). Anyway the tutorial is quite interesting, but it give some ...

Question 14

I have a PLL circuit which produces a range of frequencies. I need to design a new circuit based on another PLL synthesizer from Analog Devices using the existing design as a reference. Analog Devices ...

Question 15

I am trying to simulate a PLL using dflops as my phase detector, but the simulation seems to crash with the error "timestep too small ; trouble with dflop-instance a2" I've seen a different ...

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Questions tagged [pll]

Best approach to sweep 410-525 MHz? PLL/VCO vs ramped timer vs sweep-IC? [closed]

PLL not locking after CPLD change

Programming-free solution to Generate 50 MHz Clock from 25 MHz crystal

How do I connect a PLL sensor on transformer output with two secondary windings to a diode rectifier load?

ADF4001 Programing And Testing

Why is time constant of PLL by rule of thumb higher than the reference period?

Simulink PLL model shows different settling time than theoretical calculation

Flicker Noise and Phase Noise [duplicate]

Flicker and Noise Floor

PMU vs PLL in power system

Gowin 1K PLL Calculation Happy Accident

MAX 10 FPGA constraint problem

Si5351 Constraints I don't understand

Modeling loop bandwidth of PLL loop filter

LTspice: Timestep Too Small

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