Connection between std_logic and std_logic_vector(0 downto 0)

Question

I am trying to connect one of my VHDL blocks to a Xilinx generated block (a dual port RAM).

The problem is that the write enable of the RAM is defined as an std_logic_vector(0 down to 0) instead as a std_logic and I do not know how to connect them.

The RAM block:

component bloque_4 port( ... wea : in std_logic_vector(0 downto 0); ... ); end component;

Whereas the component that tries to write into that memory is:

component bloque_3 port( ... write_en_b3 : out std_logic; ... ); end component;

In the test bench I wrote for testing the connection I defined a signal for establishing the communication between the two of them:

signal write_en_b34 : std_logic;

So far things are great, the problem comes when I try to map the write_en_b34 signal to the wea port.

uut: bloque_4 port map ( ... wea => write_en_b34, .. );

I understand there is a type mismatch, but I do not know how to solve it. So, how could map a std_logic_vector(0 downto 0) to a std_logic??

user4574 · Accepted Answer · 2018-06-16 14:42:22Z

Do it like this.

uut: bloque_4 port map ( ... wea(0) => write_en_b34, .. );

Its perfectly OK to associate slices or elements of port with a mix of signals and constants. The only restriction is that if you associate any of the port bits then must associate them all.

Here is an example of entity foo with an 8 bit port_a.

signal s_1 : std_logic; signal s_2 : std_logic_vector(3 downto 0); ... x: foo port map( port_a(0) => signal_1, port_a(4 downto 1) => signal_2, port_a(7 downto 5) => "000" );

In the example above it would be an error if only some of the bits in port_a were not attached to a signal or a constant value. It would not be an error if none of the bits in port_a were attached, so long as the port had a default value in the entity definition.

IEEE Std 1076-2008 6.5.7 Association lists, 6.5.7.1 "A formal interface object shall be either an explicitly declared interface object or member (see 5.1) of such an interface object...In the latter cases, named association shall be used to associate the formal and actual; the subelements of such a formal are said to be associated individually. Furthermore, every scalar subelement of the explicitly declared interface object shall be associated exactly once with an actual (or subelement thereof) ..., and all such associations shall appear in a contiguous sequence within that association list." — user8352
– user8352, Commented Jun 16, 2018 at 22:53

Staszek · Accepted Answer · 2018-06-16 13:36:37Z

You can use another signal write_en_b34_v and assign to it write_en_b34. Then you can assign write_en_b34_v to Xilinx's block's input:

signal write_en_b34_v : std_logic_vector(0 downto 0); (...) write_en_b34_v(0) <= write_en_b34 (...) uut: bloque_4 port map ( ... wea => write_en_b34_v, .. );

There is probably albo another, easier way for it. You can try to assign write_en_b34_v to your block this way:

uut: bloque_3 port map ( ... wea => write_en_b34_v(0), .. );

and then use it like above. But I'm nut sure it will work.

Stack Exchange Network

Connection between std_logic and std_logic_vector(0 downto 0)

2 Answers 2

Hot Network Questions

Connection between std_logic and std_logic_vector(0 downto 0)

2 Answers 2

Related

Hot Network Questions