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I found a tutorial with a schematic where you can buy a PCB for an old computer with a 6502 microprocessor. enter image description here

I want to do this on my own with my own PCB (but I test the circuit on my breadboard first) and I have some questions for a better understanding of the design and this old technology (which is quite interesting).

  1. How does the program flow work? As I understand it, I will write the program into the 28C256 EEPROM. The EEPROM is read-only (because of WE high) and so the EEPROM will output the program data which is stored in the address range of 0x7FFF to 0xFFFF. The address bus represents the program counter and so when the program counter increases the address increases too?

  2. Why is the NAND U4C connected with the main clock? If I understand it right, the SRAM of the microprocessor is mapped in the memory region from 0x00 to 0x7FFF, because a15 is connected with the ´CS`. But what is the reason to connect the clock with the NAND?

  3. The memory space 0xC000 to 0xC00F is reserved for the I/O. So the I/O is "mapped in the same region as the SRAM" and when I write to this specific address, I will write into the SRAM and the I/O controller. Is this correct?

  4. How does this microprocessor handle an interrupt? In my understanding, the microprocessor will change the address on the bus to 0xFFFE when an event on IRQ occurs. So I have to place my interrupt code at this specific address in the EEPROM. Is that correct?

  5. It seems that I need an EEPROM programming device to write the EEPROM. Do I have to use some kind of high voltage programming or can I use a microcontroller to write this EEPROM? Otherwise, I have to buy an EEPROM programming device.

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That's a lot of questions!

  1. The address bus represents the program counter and so when the program counter increases the address increases too?

The program counter (an internal register in the 6502) is just one of the things that appears on the address bus, during an instruction fetch cycle.

  1. Why is the NAND U4C connected with the main clock?

This prevents the SRAM from starting a cycle until its inputs have been correctly set up. These inputs include the address bus, the R/W line and (for writes) the data bus.

  1. The memory space 0xC000 to 0xC00F is reserved for the I/O. So the I/O is "mapped in the same region as the SRAM" and when I write to this specific address, I will write into the SRAM and the I/O controller. Is this correct?

Yes. In this design, the writes go to both I/O and SRAM. However, the SRAM is disabled for reads from the I/O space. Note the connection between A14 and the SRAM's OE- pin.

However, note that the address range for I/O is actually 0x4000 to 0x7FFF, wasting half of the available SRAM capacity, which would otherwise run all the way from 0x0000 to 0x7FFF. But it's true that the 65C22 only needs 16 of those locations, even though it occupies half of that I/O space, from 0x6000 to 0x7FFF (A15 low, A14 high, and A13 high).

  1. How does this microprocessor handle an interrupt? In my understanding, the microprocessor will change the address on the bus to 0xFFFE when an event on IRQ occurs. So I have to place my interrupt code at this specific address in the EEPROM. Is that correct?

Not quite. The 6502 uses "vectors". The 16-bit value stored at 0xFFFE is the address of (a "pointer" to) your interrupt service routine. The actual code can be placed anywhere in memory.

  1. It seems that I need an EEPROM programming device to write the EEPROM. Do I have to use some kind of high voltage programming or can I use a microcontroller to write this EEPROM? Otherwise, I have to buy an EEPROM programming device.

That kind of EEPROM could be written by a microcontroller. For exmaple, there's MEEPROMMER for the Arduino. (Thanks to Bruce Abbott for the link.)

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  • \$\begingroup\$ Fine :). Thank you for your answers. But why do I need the NAND only for the SRAM and not for the EEPROM too? \$\endgroup\$ Commented Sep 21, 2019 at 12:07
  • \$\begingroup\$ You can't change the state of the EEPROM in this circuit (as you say, WE- is tied high), so "setup" when you're only doing read cycles is largely irrelevant. The only thing that really matters is the address in to data out propagation delay. \$\endgroup\$ Commented Sep 21, 2019 at 13:58
  • \$\begingroup\$ Hmpf...yes. Silly question. So the goal of the clock is to generate a synchronous RAM \$\endgroup\$ Commented Sep 21, 2019 at 14:42
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    \$\begingroup\$ The I/O space (in which the 6522 is active) is actually all the space from 0x6000 to 0x7FFF (with A15 low, A14 high, A13 high), but you will only use 16 bytes of this space to address the 16 registers in the 6522. \$\endgroup\$ Commented Sep 21, 2019 at 16:40
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    \$\begingroup\$ If you wanted to avoid losing those 8k RAM, you could re-route the A14 pin of the 62256 to PA6 of the 6522 instead and connect the A14 bus line to –OE only. That way you had bank-switching. The original function of PA6 as the R/–W control of the HD44780 can be left connected. You just had to take care in your programming. Another option is using the HD44780 in 4-bit mode which may be a good idea anyways as it frees up 4 additional lines on the 6522. \$\endgroup\$ Commented Sep 21, 2019 at 23:57

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