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I am playing around with a FPGA dev board featuring the Lattice ICE40-HX8K using the yosys/icestorm OpenSource toolchain, and I have noticed very odd behaviour my input pins are showing:

  • When I use a certain pin as output, the voltage level for a digital "high" is 1.2V
  • When I use the exact same pin as input, applying 1.2V to them is not enough for the FPGA to register this as a high, it is read as a digital "low".
  • Only when I use the 3.3V rail from my dev board, the input is actually registered as a digital "high".

Why is this the case? I would expect that if the output "high" is 1.2V, that the input would also work in a similar way?

If that matters, I am using a SB_IO block to implement bi-directional GPIO ports:

 SB_IO #( .PIN_TYPE(6'b 1010_01), .PULLUP(1'b 0) ) pins [15:0] ( .PACKAGE_PIN(gpio_pins), .OUTPUT_ENABLE(pin_direction), .D_OUT_0(write_data), .D_IN_0(read) );
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    \$\begingroup\$ 1.2V sounds like the VCORE voltage. which dev board/is there a chance that the I/O bank supply was accidentally routed to 1.2V or that 3.3V is actually not stable? What voltage do you read if the pull up is active? \$\endgroup\$ Commented Feb 29, 2020 at 7:43
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    \$\begingroup\$ I have the Ice40-HX8k-B-EVN board, when I measure the voltage of the port with pull up enabled it's 1.2V, but that's not enough to be recognized as a digital High. The 3.3V is stable without any ripple (checked with oscilloscope) \$\endgroup\$ Commented Feb 29, 2020 at 12:54
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    \$\begingroup\$ What voltages do you read on TP5, TP9, TP11, TP15? Do all the banks show the same behaviour (i.e. did you try to change the placement of the signal to different pads)? \$\endgroup\$ Commented Feb 29, 2020 at 13:45
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    \$\begingroup\$ @ChristianB. All of the TP you mentioned read a solid 3.3V. And yes, I tried multiple pads: C16, B16, D16, D14, D15, E16. Thanks for helping me troubleshoot this by the way, I am in way over my head here. \$\endgroup\$ Commented Feb 29, 2020 at 15:10
  • \$\begingroup\$ tbh I am running out of ideas as well. If it was a MachXOL(F)3 I would guess that the wrong IO_TYPE is selected as their I/Os are able of 1.2V BUT the ICE40-HX8K should not and the output should depend on the VCCIO only afaik. Sadly I dont have an ICE40 board anymore to check if I can reproduce that behaviour. My last calls would be to specify the IO_TYPE and to use the icecube2 toolchain as reference. \$\endgroup\$ Commented Feb 29, 2020 at 20:20

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Taking all evidence into consideration the assumption that the board (or IO bank) is broken (to some extend) seems valid.

Reasoning: It is unlikely to be a settings thing as it works as expected on the other I/O banks. The fact 3.3V is required to trigger the input is an indication that VCCIO of the bank is connected to 3.3V so it is unlikely to be a faulty or missing connection/jumper (For the MachXO3LF FPGAS I observed that current consumption over VCORE goes high if the VCCIO are not supplied correctly - maybe an indication that 1.2V is then flowing through the IO bank).

But without another board to verify this there is still a slim chance that it is something different of course.

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Have u given IO Standard while building the bit file for the fpga .U need to mention as LVCMOS12 or similar kind of voltage for this pins in constraints file.Though its an naive thing just reminding incase if u forgot to mention it.

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