0
\$\begingroup\$

I am trying to design a 3-bit counter circuit with jk flip flops that count from 0 to 7 with a clock signal and remain constant at 7 until reset. Counter counts well but it stops at six not seven.

My simulation using proteus : enter image description here

Can you guys help me please.

\$\endgroup\$
7
  • 1
    \$\begingroup\$ If you designed this circuit you should understand how it is supposed to work. You have the simulation. Observe the signals and figure out which ones have the incorrect value. It's not rocket surgery. \$\endgroup\$ Commented Apr 14, 2020 at 18:20
  • \$\begingroup\$ @ElliotAlderson I am not electronical engineer , i am computer science student. yes i designed it and it counts well , i am trying it to stop seven . \$\endgroup\$ Commented Apr 14, 2020 at 18:32
  • \$\begingroup\$ @ElliotAlderson could you help me please sir. \$\endgroup\$ Commented Apr 14, 2020 at 18:42
  • \$\begingroup\$ Counting from 0-7 is eight counts... can that be done with 3 bits? What does the J and K inputs do? Reading the chip datasheet often proves invaluable. You should try to figure this out yourself, you can do it! \$\endgroup\$ Commented Apr 14, 2020 at 18:46
  • \$\begingroup\$ Show us your truth tables. You should clean up the schematic...there is a serious rat's nest in the center. \$\endgroup\$ Commented Apr 14, 2020 at 18:51

1 Answer 1

Reset to default
1
\$\begingroup\$

You're asynchronously resetting your first FF when you get to seven. As soon as you're at 6 and flip to 7, the output of U4A resets bit 0, and you go back to 6. Disconnect U1 pin 3 (or tie high, but I note you're not driving the other set/reset lines, so I assume it's TTL or has internal pullups). Then it'll work the way you want.

\$\endgroup\$
3
  • \$\begingroup\$ where should i reset sir. \$\endgroup\$ Commented Apr 14, 2020 at 21:07
  • \$\begingroup\$ I don't know what your requirements are, but you should probably reset all 3 FFs on power up, maybe using an RC. \$\endgroup\$ Commented Apr 15, 2020 at 15:43
  • \$\begingroup\$ That, but also it looks like the reset signal for the 1st FF should go to the other two as well \$\endgroup\$ Commented Apr 12, 2022 at 16:31