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The following boolean function is given $$ f = (\neg a \land b \land \neg c) \lor (a \land b \land \neg c) \lor (a \land b \land c)$$

which should be implemented with a 8:1 mux.

Write down the truth table.

I have the following truth table (abc - variables and f the function described above)

abcf
0000
0010
0101
0110
1000
1010
1101
1111

Is this correct?

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  • \$\begingroup\$ Implementing a function using appropriately sized mux is the most straightforward thing that can be. You simply input 1s on the lines corresponding to 1s in the truth table, and use the selector inputs as an input. \$\endgroup\$ Commented Dec 4, 2020 at 18:34
  • \$\begingroup\$ @EugeneSh. I am not quite sure whether I understand it correctly, thats why I am asking. \$\endgroup\$ Commented Dec 4, 2020 at 18:36
  • \$\begingroup\$ Can you draw a truth table for MUX? While using labels d0 through d7 as the output values. \$\endgroup\$ Commented Dec 4, 2020 at 18:38
  • \$\begingroup\$ I know how a MUX is working but I am not quite sure how to implement the function above with a 8:1 MUX. I cant quite get my head around it. I know that a,b and c are there to control which of ``` dx ``` is chosen to be the output where x is an element of {0,1,..,7}. \$\endgroup\$ Commented Dec 4, 2020 at 18:42
  • \$\begingroup\$ I am trying to guide you to understanding. So can you draw such a table? If you can, then what should you do to make this table equivalent to your function? You will need to assign the ds the corresponding values. \$\endgroup\$ Commented Dec 4, 2020 at 18:44

1 Answer 1

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Yes, what’s shown in your table is correct. A mux (this is, a lookup table) is a valid way of making logic. It’s how FPGA logic works.

You can also express the function as a sum of products, as three 3-input AND gates followed by a 3-input OR. This is how it would work in programmable logic like a CPLD, or in an actual custom ASIC. This is more area-efficient than a full lookup table.

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