I've tried a zillion different ways to get the lattice iCECube2 tools to find a generated clock. How do I specify the .sdc file to see the output of baudgeninst, which is used as a 115,200 baud clock to the test junk register? I think this is causing problems later in the design where the tool can't place a not-very-complicated block of logic. I've removed the larger block from below code. The code below happens to build, but it still can't find the clock. When I include the larger block, the code fails at placement. I suspect not knowing about the baud clock is the reason.
top.sv:
module drotop(input rstb, input clk, // board clk input dclk, // dro clk input ddat, // dro in output dclkout, output ddatout, output tx, // uart out input rx, // uart in output debug, output [7:0] dbus, output [7:0] led ); logic [7:0] junk; logic baudclk; baudgen baudgeninst(clk, baudclk); always @(posedge baudclk, negedge rstb) begin if (!rstb) junk <= 8'h0; else if (baudclk) junk <= junk + 1; end endmodule module baudgen(input clkin, output clkout); // From https://www.fpga4fun.com/SerialInterface2.html parameter freq = 12_000_000; // 12MHz parameter baud = 115200; parameter width = 16; parameter incr = ((baud<<(width-4))+(freq>>5)) / (freq>>5); logic [width:0] acc = 16'b0; always @(posedge clkin) acc <= acc + incr; assign clkout = acc[width]; endmodule prj.sdc:
# Clocks create_clock -period 83.333 [ get_ports clk ] ;## 12.0 MHz # I've tried various versions of this type of thing with get_pins, get_nets, get_ports, # identifier names in top level, identifier names between modules, net names inside the # the module as found in reports, vertical bar '|', slash '/', curly braces, etc. # Error looks like: # "c:/lattice/constraints/prj.sdc":11:0:11:0|Clock source [get_nets {baudgen|acc_derived_clock[16]}] not found in netlist: create_generated_clock -source [get_ports clk] -divide_by 104 [get_nets {baudgen|acc_derived_clock[16]}] create_generated_clock -source [ get_ports clk ] -divide_by 104 [get_nets {baudgen|acc_derived_clock[16]}] create_generated_clock -source [ get_ports clk ] -divide_by 104 [get_nets {drotop|baudclk}] create_generated_clock -source [ get_ports clk ] -divide_by 104 [get_pins {baudgen|clkout}] create_generated_clock -source [ get_ports clk ] -divide_by 104 [get_pins {baudgeninst|clkout}] 