A suboptimal layout will take more time than a good one once you take into account that you need to revisit it at some point. Once you get all the 'best practices' in your muscle memory, a good layout won't take more time to route. But I get it, I have done projects in small companies that where so time constrained, the PCB design had to be done within 1 day. Routing at '11 in the evening is just that much harder ;)
I have made a W5500 design that is tested working on STM32 and ESP. I have never experienced this reset issue/workaround. Heck, I didn't even have code running on the STM32 but the W5500 was being recognized by the network and link and act. leds working as expected. The only time this didn't work is when the firmware designer forgot to init the pins correctly and the W5500 was being kept in reset. That was an easy fix for a change.
I'm using a ferrite bead + capacitance filter for the AVDD, that has its own little plane next to and under the chip. The RX/TX pairs keep on top layer almost all the time, except for one unfortunate jump. The GND plane is extended to layer 3 for this section of the pair just to be sure. I'm using low capacitance TVS clamps on the data lines. This can be really important in certain environments. The routing becomes a bit less nice, but I'd say it's within limits. I'm using a oscillator instead of a crystal, but that shouldn't matter too much. The shield and internal magnetics ('wire' side) of the connector are AC grounded using a high-voltage MLCC. The routing is really compact, and manages to stay about as wide as the connector itself. This way you can kind of 'stack' them next to each other if your design ever needs another port. A double sided component layout would have made this layout even better and more compact, but that was going too far for this particular project.
The only main difference between our schematic I notice is you leave reserved pins open, I read in some reference example that you can pull them to ground to be sure. Also ofcourse the oscillator/crystal and TVS clamps. But that wouldn't matter too much unless your crystal is not starting properly, but I don't really suspect that. My Pmode pins are all pulled up, just as in your schematic

I hope this example is in any way useful to you
Just a thought: whenever the issue presents itself, measure the clock source and supply lines for any abnormal behavior. For different reasons people already stated your circuit could experience undefined/unexpected behavior