Verilog in Vivado - DRC MDRV-1 Multiple Driver Nets Error

I am writing code that behaves as a rudimentary register file. I have created the register file as a module reg_file.v. The code instantiates a module, describing a register with loading capabilities, using generate with a simple 'for' loop.

When trying to implement the register module, I get the forementioned error. Here is the register module:

 `timescale 1ns / 1ps module simple_register_load #(parameter N = 4)( input clk, input load, input [N - 1:0] I, output [N - 1:0] Q ); reg [N - 1:0] Q_reg, Q_next; always @(posedge clk) begin Q_reg <= Q_next; end // Next State logic always @(load, I, Q_reg) begin if (load) Q_next = I; else Q_next = Q_reg; end // Output logic assign Q = Q_reg; endmodule 

Within the "Next State Logic" the line associated with Q_reg <= Q_next gets flagged for the error.

always @(posedge clk) begin Q_reg <= Q_next; end 

I have searched the forums and have found others with similar issues, and they all point to modifying an output in multiple 'always' statements. But here, I only modify Q_reg in one of the 'always' blocks. Q_next is also only modified in one 'always' block. I am puzzled.

This is the register file module code for reference:

`timescale 1ns / 1ps module reg_file #(parameter N = 4, BITS = 4)( input clk, input [N - 1:0] address_w, address_r, //write address, read address input WE, //write enable input [BITS - 1:0] data_w, // write data output [BITS - 1:0] data_r // read data , input read_write_sel ); wire [2**N - 1:0] address_w_dec, address_r_dec; wire [BITS - 1:0] reg_data; // WRITE PORT decoder_generic #(.N(N)) write_decoder( // N x 2^N decoder .w(address_w), .en(WE), .y(address_w_dec) ); // READ PORT decoder_generic #(.N(N)) read_decoder( // N x 2^N decoder .w(address_r), .en(~WE), .y(address_r_dec) ); // REGISTERS genvar k; generate for(k = 0; k < 2**N; k = k + 1) begin: register simple_register_load #(.N(BITS)) R( .clk(clk), .load(address_w_dec[k]), .I(data_w), .Q(reg_data) ); assign data_r = address_r_dec[k] ? reg_data : 'bz; end endgenerate endmodule 

The errors if I run for N = 1 (generate 2^N = 2 registers):

[DRC MDRV-1] Multiple Driver Nets: Net nolabel_line34/register[1].R/Q[1] has multiple drivers: nolabel_line34/register[0].R/Q_reg_reg[1]/Q, and nolabel_line34/register[1].R/Q_reg_reg[1]/Q.

[DRC MDRV-1] Multiple Driver Nets: Net nolabel_line34/register[1].R/Q[2] has multiple drivers: nolabel_line34/register[0].R/Q_reg_reg[2]/Q, and nolabel_line34/register[1].R/Q_reg_reg[2]/Q.

[DRC MDRV-1] Multiple Driver Nets: Net nolabel_line34/register[1].R/Q[3] has multiple drivers: nolabel_line34/register[0].R/Q_reg_reg[3]/Q, and nolabel_line34/register[1].R/Q_reg_reg[3]/Q.

I feel like there is a really simple issue that I am missing, and I would be very grateful if someone could point it out.