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I am using the Basys 2 Spartan-3E FPGA board with Xilinx. I need the pmod i/o to be at 1.8v so I am using LVCMOS18 IOSTANDARD.

You can find all of the IOSTANDARD's available for Spartan-3E in this document.

Whenever I try to compile my project it always errors out on the Place & Route phase that says:

ERROR:Place:864 - Incompatible IOB's are locked to the same bank 0 Conflicting IO Standards are: IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR List of locked IOB's: mclk ERROR:Place:864 - Incompatible IOB's are locked to the same bank 3 Conflicting IO Standards are: IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = OUTPUT, DRIVE_STR = NR List of locked IOB's: LEDs<7>

I have done some research on that error and I believe it means that there are different IOSTANDARD's on the same bank. The pins that I directly set are on bank 1 but the conflicts are on bank 0 and bank 3. When I remove the IOSTANDARD from the pmod i/o it compiles successfully but those pins are not 1.8v then.

My constraints file looks like:

# clock pin for Basys2 Board NET "mclk" LOC = "B8" ; # Bank = 0, Signal name = MCLK NET "mclk" CLOCK_DEDICATED_ROUTE = FALSE; # Pin assignment for LEDs NET "LEDs<7>" LOC = "G1" ; # Bank = 3, Signal name = LD7 NET "LEDs<6>" LOC = "P4" ; # Bank = 2, Signal name = LD6 NET "LEDs<5>" LOC = "N4" ; # Bank = 2, Signal name = LD5 NET "LEDs<4>" LOC = "N5" ; # Bank = 2, Signal name = LD4 NET "LEDs<3>" LOC = "P6" ; # Bank = 2, Signal name = LD3 NET "LEDs<2>" LOC = "P7" ; # Bank = 3, Signal name = LD2 NET "LEDs<1>" LOC = "M11" ; # Bank = 2, Signal name = LD1 NET "LEDs<0>" LOC = "M5" ; # Bank = 2, Signal name = LD0 # Loop Back only tested signals NET "spi_si" LOC = "B2" | DRIVE = 2 | IOSTANDARD = LVCMOS18 | PULLDOWN ; # Bank = 1, Signal name = JA1 NET "spi_so" LOC = "A3" | DRIVE = 2 | IOSTANDARD = LVCMOS18 | PULLDOWN ; # Bank = 1, Signal name = JA2 NET "spi_cs" LOC = "J3" | DRIVE = 2 | IOSTANDARD = LVCMOS18 | PULLDOWN ; # Bank = 1, Signal name = JA3 NET "spi_sck" LOC = "B5" | DRIVE = 2 | IOSTANDARD = LVCMOS18 | PULLDOWN ; # Bank = 1, Signal name = JA4 NET "sw0" LOC = "P11"; # Bank = 2, Signal name = SW0

How do I fix these conflicts?

The Basys2 has the CP132 package. Here is the chip diagram and bank schematic: Basys 2 Bank Schematic and CP132 Package

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3 Answers 3

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As you have surmised, you get errors when you have incompatible IO standards in the same bank. It's best to know exactly how this stuff works, because the tools will gladly give you a bitfile that ends up burning out your FPGA due to incompatible IO.

As you posted above, we can consult the Xilinx datasheet for the device family, DS312. Supported IOSTANDARDs are set by the VCCO of a given bank. Notice that input and output are supported only when the number in the IOSTANDARD matches the voltage; input is supported for anything equal or lower.

Spartan 3E IOSTANDARDs

Now look at the last page of the Basys2 schematic.

Basys2 FPGA power

It appears that all the VCCO's are connected to 3.3 volts. This means that you can do LVCMOS33 input/output, and all other LVCMOS input. You cannot do the LVCMOS18 output that you would like to do. If the UCF was set up for LVCMOS33 on all the other pins, the tools would recognize the impossibility of what you're trying to do and give an error. As it stands, the IOSTANDARDs in the UCF are blank, which default to LVCMOS25, and so the tools detect a mismatch.

You might be wondering why Diligent set up their UCF the way they did, since everything defaults to 2.5 volts when the board is actually 3.3. I don't know. The point is that the FPGA accepts pin settings without complaint, as long as the settings are consistent within the bank; it's up to you to make sure the external voltage matches. So you could "fix" your problem by setting a whole bank to LVCMOS18, but then you would probably fry your SPI device with 3.3 volts.

The way I see it, you have several options.

  1. Serious surgery on the Basys2 board, changing the VCCO's appropriately. Probably not worth it.

  2. External level shifting circuitry. You can read the serial input just fine, but the other SPI signals have to be shifted down. You can either do this with something like an 74LVC series logic chip, some series FETs, or just resistor dividers.

  3. Current limiting resistors. This method relies on the clamping diode in the target device to limit the voltage, and the resistor limits the current to a safe level. There are resistors out to the PMOD pins, but they're probably not enough. Do due diligence if you choose this option.

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  • \$\begingroup\$ How do you go about "setting a whole bank to LVCMOS18"? Right now every pmod pin in JA is set to 1.8v but still giving 3.3v tolerance which from everything that I read but that comment seems the only level the board offers. I do happen to have some 74LVC chips and just plugged one into my breadboard so this may be the only option. The scare factor is more present to me now knowing that the tools don't safeguard me from the real world. I am still a bit of a noob when using outside chips and where to use resistors, etc so hopefully the extra layer doesn't trip me up. \$\endgroup\$ Commented May 23, 2013 at 3:23
  • \$\begingroup\$ "You cannot do the LVCMOS18 output that you would like to do. That's why the tools are giving you an error." It's correct that LVCMOS18 can't be used with this board as is. But that doesn't explain the error. The tools know nothing about the board schematic. If you ask for LVCMOS18 they will assume you are providing an appropriate VCCO. \$\endgroup\$ Commented May 23, 2013 at 3:28
  • \$\begingroup\$ "because the tools will gladly give you a bitfile that ends up burning out your FPGA due to incompatible IO" is not strictly true. There is no harm to the FPGA in selecting a different I/O Standard to the Vcco for that bank. The table you quoted shows that you can use a I/O standard as an input with a higher voltage Vcco. Any damage to the FPGA would be from applying a voltage to an I/O that exceeds the absolute maximum ratings specified in the datasheet. The tools have no idea what you physically hook up to the chip and therefore can not be responsible for "burning out your FPGA". \$\endgroup\$ Commented May 23, 2013 at 4:17
  • \$\begingroup\$ @Amoch, yes, you're right. I wanted to give a stern warning but went too far. When I get a chance, I'll give the whole thing another revision. \$\endgroup\$ Commented May 23, 2013 at 16:19
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2.5 V is the default. If you don't define the voltage, that's what the software uses.

Multiple voltages in a bank is not fixable. You must use the same I/O voltage for all the pins on a bank. Also all I/O power pins for a bank are connected together.

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For starters, you have some errors in your pin assignments.

LEDs<2>, Pin P7, is bank 2 and not 3. spi_si, pin B2, is Bank 3 and not 1. spi_so, pin A3, is Bank 0 and not 1. spi_cs, pin J3, is Bank 3 and not 1. spi_sclk, pin B5, is Bank 0 and not 1.

I never encountered a problem with the software defaulting to 2.5v, as Brian Carlton said. It may be a problem and I just haven't ran into that issue.

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  • \$\begingroup\$ Those ucf comments come straight from the Digilent .ucf download for Basys 2 so I was not firm on whether they were correct in the first place. I just posted the Basys 2 Schematic and CP132 package and will double check. \$\endgroup\$ Commented May 22, 2013 at 22:20
  • \$\begingroup\$ Alright, those bank numbers are correct from what I have looked at. I have added IOSTANDARD = LVCMOS18 to mclk and LED<7> and it compiles but the i/o is still 3.3v. I am using a multimeter and measuring from the GND on the PMOD connector. Also I am not sure if there is a way to change VCC from 3.3v \$\endgroup\$ Commented May 23, 2013 at 2:19
  • \$\begingroup\$ You must connect the VCCIO pins for that bank to an appropriate power rail. +3.3v for LVTTL, +1.8V for LVCMOS18. Otherwise bad things could happen. \$\endgroup\$ Commented May 23, 2013 at 3:03
  • \$\begingroup\$ As mng mentioned I think the only way to set VCCIO is to Frankenstein the board and I do not know where to begin on that... How did you figure out the bank numbers so quickly? It took me a while to go about matching it up from schematic to chip. I guess level shifting is the only sane option. I am wondering what is the better option: level shifting on SPI lines going to the FPGA, or the data coming into the SPI chip (which would be 3.3v coming out of the SPI chip). I am planning to run at the 10 Mhz spec of the MCP23S17 port expanding chip. \$\endgroup\$ Commented May 23, 2013 at 3:34
  • \$\begingroup\$ There is an ASCII file on the Xilinx website that contains all of that info. Basically, each line lists the pin name, bank, function, direction, and pin number for a variety of packages. It is intended to be read into various programs and spreadsheets, but it works well for this. It is called the "Spartan-3E FPGA ASCII Pinouts and Excel Footprints", but here is the link: xilinx.com/support/documentation/data_sheets/s3e_pin.zip \$\endgroup\$ Commented May 23, 2013 at 3:57

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