Ethernet port as a signal generator

Is it technically possible?

No. Highly specialized hardware, relatively specific coupling, and a very limited set of amplitudes actually imposable on the line make that infeasible.

Don't get me wrong: a modern driver probably has gain control to do more than the "PAM 5" (even that is a bit of a stretch) that Ethernet can do, but there's a difference between "can adjust power level to match line length" and "able to generate arbitrary amplitudes on the fly".

I ideally want to create a 1 GHz I/Q signal over good network card,

Not happening, even remotely. Gigabit Ethernet uses four lanes of PAM-5, each with a 125 Mbd, so you get at most a bandwidth of 62.5 MHz (via the standard, not including the side band artifacts).

But again, you don't even get to define that, because the line drivers are designed for PAM-5 and not some general-purpose DACs; in fact, you can be pretty sure that without design-house knowledge, you couldn't do anything but the trellis-coded tetradimensional PAM-5, i.e. you can't define what's on the lanes in an arbitrary manner. There is a temporal and a cross-lane dependency on data, and you'll need to be tricky already to make a 1000Base-T card transmit anything into an empty load – echo cancellation would wonder what is up with the returning channel impulse response.

Also, think about it: A reasonable signal generator for 1 GHz bandwidth would need to consume 2 GS/s worth of samples, and throwing the number "8 bit per sample" in the room, you'll find that the PCIe connection of your gigabit ethernet card won't be up to the 16 Gb/s that you need for signal generation.

If the computer hardware can't support it, I figure it could still be possible in theory, to at least send square waves

No, Gigabit Ethernet network cards are built to not do that, see trellis-code modulation; as said, you don't get to choose the waveform you send freely.

(in 10 GBase-SR and similar OOK fiberoptical networking standards, you do get an "idle" rectangular wave pattern, to keep the clock synchronization, but it's again nothing you can freely choose)

This could then be repeated from a different port/computer, and the two signals used as I/Q signals for a vector signal generator.

Uh, you realize you forgot that you would need phase synchronization for that, even if your idea worked.

Even tens to hundreds of MHz would be a win.

To keep DACs at hundreds of Megasamples per second running, you'll need a relatively modern, and expensive, FPGA with appropriate buffering and a high-speed interface to your CPU (that's how SDR devices like Ettus USRP X310 do it, and some cellular basestations, some radars, some commercial measurement-grade signal generators), or a complete ASIC-based devices (other base station hardware, some military radars, high-bandwidth arbitrary waveform generators…).

Note that the problem is absolutely not that the world can't produce high-speed DACs with > 100 MHz bandwidth for cheap – every wireless chipset that does WiFi with 160 MHz channels has such – it's that getting this much data per second into the DAC requires either the high-rate data to be produced in the very same chip (as is the case with Wifi chipsets), or an extremely high-rate digital external bus. Since DACs' job is to consume samples at a constant rate, you need a buffer that can be read at the high constant rate, and written to in bursts from whatever packet bus you use to connect this to computer-style hardware: PCIe, USB and Thunderbolt all are "bursty" buses, so that you need to re-fill that buffer from say your CPU or RAM in bursts, for it to be drained at a constant rate by the DAC. This requires either highly specialized ASICs (and building an ASIC is expensive if done for low volume) or fast FPGAs (and these are expensive). That's why multi-Gigasample arbitrary waveform generators that you can connect to your PC come in prices that are in the order of annual engineer salaries, and not at the price point of a Gigabit Ethernet or Wifi card: To enable low prices, you need to build specialized ASICs as cheaply as possible, and to sell them literally millions of times. Sadly, this specialization does not allow for adding a "direct full-rate digital IQ from PCIe to DAC buffer in a continuous stream" chain, usually – the high-speed digital interface would just be too large (in expensive silicon area) and power-hungry to drop it in for that purpose. Within limits, such direct-IQ features do exist, for spectrum compliance testing purposes, especially in wireless equipment, but they allow for things like a single OFDM frame to be defined by the host – exactly because you can "slowly" load that through the slower paths that are usually just for Ethernet packet data and configuration, and then play it back through the DAC once.

I doubt it: Ethernet is a specialized medium, and line control, framing, etc. are built in to the interface (the MAC). Needless to say, you'd also need the driver-level hardware documentation, and a custom driver to interface Windows at least, to whatever your user program is doing (easier on *nix with root access, or drivers at various levels).

From Chester's comment: along those lines, your best bet may be a project like DPDK, which looks like it offers a framework to do this sort of thing with supported devices. Still, seems a stretch.

There are a few devices either documented (reluctantly/obscurely by the manufacturer) or reverse-engineered (e.g. code analysis of blob drivers, logging IO transactions) to the point where open-source drivers exist, but such devices are few and far between, and it's even less likely that such a device is also flexible enough to be used in this way. (Not to say it can't happen, but you'll have to search them out and dig into the docs on each one.)

But there does exist simple hardware with some intriguing possibilities:
Spoofing Cell Networks With a USB To VGA Adapter | Hackaday

That's still only going to get you harmonic (aliased) synthesis at such frequencies, but as signal for a modulator e.g. ADRF6755, LTC5589, etc., that might be a route. But it's going to be a lot less off-the-shelf at that point, and a regular SDR, or proper I/Q instrument, would be better.

I do NOT claim this answer fully satisfy OP's demands. It is meant as inspiration for what you actually can do.

This answer is based on the comment of user 比尔盖子

According to 40.6 of the IEEE 802.3-2005 all gigabit PHYs must support a 125 MHz test signal:

For this card you can learn to setup test mode 2 125MHz signal using Reg 0x9 = 0x5B00

User 比尔盖子 specifically mentions TDR test capabilities. TI provides register level documentation. The TDR registers can initiate a step (pulse). You can possible convert that to a continuous signal by initiating the step in a loop using "no operation" instructions to ensure the delay of the frequency you wish. Also, take a look at SolarFlare's NICs featuring a FPGA meant to be reprogrammed for the customer's need. It is based on open source software. Finally, a simple low pass filter can change the signal to a sine wave.

I leave it to other users to provide proper documentation for the very popular Intel and RealTek NICs. Especially, it could be pretty nice to learn about Broadcom's BCM54213 Gigabit PHY used for the very well documented Raspberry Pie 5.

I feel sure other users can figure out even better solutions :)

As an analogy, it is possible to store/transmit a photograph as sensible English text, but that is not remotely the easiest way to send a photo. If you're looking for a mathematical existence proof, then Steganography is an interesting field. If you're looking for a parlor trick, it works. It might work for some sort of covert communication. But it isn't a sensible way to store photographs.

The wire and insulation and such of an Ethernet port are physically capable. But everything that makes it an "Ethernet port" instead of just a wire is working against you.

Yes, I know that it's made for primarily digital communication, but if computer hardware can somehow support it, analog signals should be able to travel over the cable easily, even in the low GHz frequency range before higher modes become a problem.

The hardware that takes data from an Ethernet port and produces a fast analog output is 4 chips: Ethernet PHY, an FPGA, a DAC, and a PMIC. These would fit on the area of a large postage stamp, and will cost not very much - maybe $25 qty 1k?

Power it from a battery and you got a nice, isolated source of signal. The FPGA doesn't need to be particularly powerful - it only needs to implement an RMII Ethernet MAC, a buffer - whether a FIFO or a circular buffer, and/or a Cordic where the ethernet packets carry phase information, and the Cordic generates the subcarrier, and the DAC interface.