FIFO Not Storing Sequential Data Correctly in ICE40UP5K FPGA – Possible Timing Issue

That has got to be some of the strangest FIFO code I've ever seen. I'm not even going to try to debug it; it really needs a complete rewrite.

Muxing the clocks to drive a single counter makes no sense at all.

Given that you have separate write and read clocks, and separate write and read ports on your RAM, it would make a whole lot more sense to have one process for writing and one process for reading, each with its own address counter, and a simple pair of signals that allow each one to signal the other when it reaches its maximum count — with appropriate clock-domain-crossing precautions on those signals.

Since I'm currently on a train with nothing better to do, here's what I would suggest. First, here's a generic module that I use for getting a signal across a CDC, xd_sync.v. It also does edge detection in the destination domain, providing pulses for rising, falling or both edges.

module xd_sync #( /* number of resync FFs before edge detector */ parameter STAGES = 3 ) ( input clock, input din, output dout, output dout_d, output any_edge, output rising, output falling ); /* The ASYNC_REG property is specific to CDCs on Xliinx parts */ (* ASYNC_REG = "TRUE" *) reg [STAGES:0] din_d; always @(posedge clock) begin din_d <= {din_d[STAGES-1:0], din}; end assign dout = din_d[STAGES-1]; assign dout_d = din_d[STAGES]; assign any_edge = dout ^ dout_d; assign rising = dout && !dout_d; assign falling = !dout && dout_d; endmodule 

(Note that the code from here on is completely untested, but I believe it should work.)

Second, let's define an address counter that should work for either writing or reading. Note that by making RESET_STATE a parameter, we can control which counter is active following a reset.

module fifo_address #( /* address width */ parameter WIDTH = 12, /* state of "done" on reset */ parameter RESET_STATE = 0 ) ( input clock, input reset, input start, input enable, output [WIDTH-1:0] address, output done ); /* Extra bit in counter serves as "done" state */ reg [WIDTH:0] counter; wire [WIDTH:0] reset_value = RESET_STATE ? {1'b1 {WIDTH-1{1'b0}} : 0; wire start_pulse; /* Handle "start" as an asynchronous input, looking for a rising edge */ xd_sync xd_sync_1 ( .clock (clock), .din (start), .dout (), .dout_d (), .any_edge (), .rising (start_pulse), .falling () ); always @(posedge clock) begin if (reset || start_pulse) begin counter <= reset_value; end else if (enable && !counter[WIDTH]) begin counter <= counter + 1; end end assign address = counter[WIDTH-1:0]; assign done = counter[WIDTH]; endmodule 

Now we can define the top-level dual-clock ping-pong FIFO module. Note that this is much simpler than a fully asynchronous dual-clock FIFO would be. For that, you'd probably be better off using a FIFO generated by your vendor's tools.

 module dc_pingpong_fifo #( parameter addr_width = 12, parameter data_width = 24, parameter max_data_count = (1<<addr_width) ) ( input rst, input write_en, input wclk, input [data_width-1:0] din, input rclk, output [data_width-1:0] dout, output full, output empty, output direction // 0 is write, 1 is read (not actually used) ); wire [addr_width-1:0] waddr; wire w_done; wire [addr_width-1:0] raddr; wire r_done; // RAM module for the FIFO ram #( .addr_width (addr_width), .data_width (data_width) ) ram_inst ( .din (din), .write_en (write_en), .waddr (waddr), .wclk (wclk), .raddr (raddr), .rclk (rclk), .dout (dout) ); /* Write address generator */ fifo_address #( .WIDTH (addr_width), .RESET_STATE (0) ) fifo_address_write ( .clock (wclk), .reset (rst), .start (r_done), .enable (write_en), .address (waddr), .done (w_done) ); /* Read address generator */ fifo_address #( .WIDTH (addr_width), .RESET_STATE (1) ) fifo_address_read ( .clock (rclk), .reset (rst), .start (w_done), .enable (dir), .address (raddr), .done (r_done) ); /* Direction logic */ assign full = w_done; assign empty = r_done; assign direction = !r_done; endmodule