Based on the comments to the original question I assume that you generate PWM and you need to toggle some GPIO at the same time when you PWM signal goes low (falling edge). It is pretty simple. Select timer with two or more outputs (for example TIM3). Let him generate PWM on one channel (exactly "PWM edge-aligned mode"). Then value in compare register define "compare event" - moment when PWM goes low (your falling edge). Configure second channel in "output compare toggle mode" and write the same value in its compare register. When counter reaches value in this compare register(s) it toggles timer output. Then your falling edge and toggle will be generated at exactly same time.
When you need to change duty cycle, you have to write new value into two compare registers (one controlling PWM, second controllig toggle, both need the same value). Because there is a risk of a race condition, you should to activate "update disable" feature (UDIS bit in TIM3.CCR). Then write both values into compare registers and then clear "update disable". Of course both channels should have buffer enabled (as is usual with PWM).