Capacitor in series needs a charge path but a discharge path also. The Rb ensures both part of this condition.

Without Rb the capacitor is charged through base only during positive cycle. But nothing allows to discharge the cap back during negative cycle. So the cap becomes fully charged after few periods and no signal passing.

In the first picture (2.16), no source is shown so the DC level is unknown, but as you refer to,

In the preceding circuit it is assumed that the signal source has a DC path to ground.

some kind of DC path is existing.

In figure 2.17, where a capacitor is explicitly shown, some kind of DC bias path is required. It could have been a standard voltage divider between Vcc and Vee with the base connected inbetween.

The capacitor prohibits the flow of DC current so if it is necessary to establish a DC operating point, some kind of DC bias path is required. In this case a single resistor is used. If no base current is flowing no collector current will flow. Base current would only flow in the beginning unttil the capacitor is charged up.

Ignore the emitter follower for a moment, and focus only on the capacitor and some source of input signal:

^{simulate this circuit – Schematic created using CircuitLab}

Ask yourself what is potential \$V_B\$ at node B? The answer depends on what initial charge the capacitor has. If C1 starts completely discharged, with no potential difference between A and B, then the answer is:

$$ V_B = V_A + 0V = V_A $$

\$V_B\$ follows \$V_A\$. If \$V_A\$ rises by 1mV, then so will \$V_B\$, and if \$V_A\$ falls by 1mV \$V_B\$ will also fall by 1mV. There's no offset between A and B, so the capacitor is pointless here. You could achieve this behaviour by directly connecting B to A.

The utility of the capacitor is evident when the average DC potentials at A and B are different, creating a potential "gap" that needs bridging. Let's say that \$V_A=+5V\$ average, and \$V_B=+7V\$ average, then you have a gap of 2V to bridge. Charge the capacitor to 2V (more positive at its right end), so now the equation becomes:

$$ V_B = V_A + 2V $$

You still have \$V_B\$ following \$V_A\$ as it changes, but offset by 2V.

The purpose of the capacitor is to "bridge the DC voltage gap" between potentials \$V_A\$ and \$V_B\$ at nodes A and B, while permitting any change in potential \$\Delta V_A\$ to appear at B as an equal change \$\Delta V_B\$. This is called "AC coupling", or you could think of it as "DC blocking", if you like.

It works because A and B can have different average DC potentials, which the capacitor "bridges" by developing a long-term average DC charge and voltage according to \$Q=CV\$, but crucially any changes in potential at A are "copied" to B.

However, you must somehow get the capacitor to charge to 2V (or whatever is the average DC potential difference) in the first place. Clearly this is not possible above, because current \$I_1=0\$. There's no path to permit the DC current necessary to charge the capacitor to any DC potential difference other than zero.

We must somehow coerce the potential at B to whatever long-term value we desire, usually by using a resistance to that very potential:

^{simulate this circuit}

Here we have a sinusoidal AC input at A provided by V2, centered at an average of +5V DC provided by V1. We want the average potential at B to be +7V DC, which we set by providing a path for DC current via R1 to a source of +7V, thanks to V3.

Start by assuming that there's no AC signal, the amplitude of V2 is zero. Also, the capacitor starts discharged. In this state, there is a DC potential difference of \$7V-5V=2V\$ across R1, causing current \$I_1\$ to flow, which will slowly charge C1. In this DC context, this is a simple RC arrangement in which the capacitor voltage rises exponentially to 2V (orange), and DC current (blue) eventually diminishes to zero:

Any fluctuations at A will still be copied to B, though, and eventually you find that fluctuations at B are centered 2V higher than those at A, because the capacitor's DC voltage eventually reaches a steady 2V:

This behaviour depends on a path existing for DC charging current through the capacitor, a path provided by R1, to a biasing potential V3. Without DC current through C1 to initially charge it, you have no idea what that initial charge is, and you can't predict the "center" average DC potential at B. For this reason, you never see the arrangement on the left below; rather, you'll find some variation on the arrangement to the right:

^{simulate this circuit}

Op-amp input resistance is infinite, or at worst, very very large, and bias current \$I_{BIAS}\$ is zero, or poorly defined. Consequently, without R1 and some biasing potential, the average DC value of \$V_B\$ is unknown, entirely dependent upon the ambiguous state of charge of C1.

In the context of your question, the thing connected to B is not an op-amp, but an emitter follower. Without DC biasing (left) and with DC biasing (right), it looks like this:

^{simulate this circuit}

The voltmeters show DC (quiescent) potential at the transistors' bases. On the left, without biasing, clearly DC quiescent base current has charged the capacitor with -11.5V of DC charge. Consequently, Q1's base is near the negative supply potential, and its output (emitter) will be stuck near -12V. Ideally we would like the output to be nearer to 0V, the middle of the -12V to +12V range. This is achieved on the right by biasing base potential using R2 to 0V.

Here are the outputs, emitter potential \$V_{E1}\$ (blue, no biasing) and emitter potential \$V_{E2}\$ (orange, biased near ground):

In your question you called \$R_B\$ (R2 here) a "base resistor". Using that name is misleading, because "base resistor" typically describes a resistor in series with the base, whose role is to limit base current in a common-emitter scenario:

^{simulate this circuit}

The current-limiting role of R9 is very different from the biasing role of R2 in the prior circuits. \$R_B\$ and \$R_2\$ should be called "biasing" resistors, not "base" resistors. R9 here may be called a "base resistor".

The magic of The Art of Electronics

I find it hard to imagine what my life would be like if I had not encountered the incredible book by Mr. Horowitz and Hill in the 1980s, and later, Mr. Tom Hayes' accompanying Student Manual. They showed me what I had intuitively sensed - that circuit design could be not as boring as it was presented in textbooks and lecture halls, but rather interesting and engaging, even romantic.

The most valuable quality of these books is not that they give us a lot of knowledge but that they make us think and ask questions like this. That is why I have never seen them just as books but as "idea stimulators." In the days when there was no (mobile) internet, I carried this book, heavy as a brick, with me on vacations to the sea and mountains. The scenario was always the same - I would start reading and after the first few paragraphs, I would stop and start thinking about the idea behind the circuit. That is how I never managed to finish reading them...

After this emotional intro, let's try to uncover the idea behind these two AoE circuits.

What is actually biasing?

Simply put, biasing means adding a constant voltage to the input varying voltage. In this way, we force the transistor to start operating even at zero input voltage. Let's now see how it is implemented in amplifier circuits.

Direct coupling

Base biasing

"Lifting" voltage source: In an emitter follower with a (positive) single power supply, we can do this from the base side by "lifting" the input voltage with a bias voltage. For this purpose, we connect the bias voltage source Vbias in series to the input voltage source Vin. Note that the bias current Ibias flows through the input source; it does not flow through +Vcc.

^{simulate this circuit – Schematic created using CircuitLab}

"Lifting" diode: In practical amplifier circuits, "floating" diode elements can "produce" Vbias. Note that in this case, Ibias is produced by +Vcc and it does not flow through Vin.

^{simulate this circuit}

Emitter biasing

In a emitter follower with a split power supply, we can bias the transistor from the emitter side but through current (because the emitter voltage is "movable" and it follows the changes in the input voltage). This technique is called "self-emitter biasing" because the transistor is forced to adjust its base current so that to pass the same current through itself.

Emitter resistor: The simpler implementation of this bias technique is through a resistor Re connected between the emitter and negative power supply -Vee. Note that in this NPN configuration, Ibias is produced by the negative power supply and it flows through Vin; in the case of a PNP implementation, Ibias would be produced by the positive power supply.

^{simulate this circuit}

Emitter current source: A more sophisticated biasing implementation is through an emitter current source. Now the bias current is absolutely constant and dies not vary when the input voltage varies.

^{simulate this circuit}

Emitter voltage source: If we try to put a voltage source in the emitter out of curiosity, the output voltage does not change.

^{simulate this circuit}

Capacitive coupling

No current path

In AC amplifiers, a capacitor couples Vin and the base. However, a path for the bias current must still be provided. Otherwise, the capacitor will charge to its maximum value and current flow will cease.

^{simulate this circuit}

Added closing resistor

This is the role of the resistor Rb - to close the path of Ibias.

^{simulate this circuit}

Visualized voltage drop

Note that Ib causes a voltage VRb = Ibias*Rb to appear across Rb, which adds to the input voltage. Let's replace Rb with a voltmeter with the same internal resistance to see this undesired voltage drop.

^{simulate this circuit}

This is a problem in op-amps with significant input bias currents (see my answer to a related question).