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I know that the expression itself can easily be implemented with an AND and a NOR gate.

  • X = A AND B
  • Y = C NOR X

My CMOS gate implementations consist of 5T for my AND gate, and 4T for my NOR gate. Combining these together gives me the working functionality for the expression. It satisfies this truth table:

 A B C | Y ------|--- 0 0 0 | 1 0 0 1 | 0 0 1 0 | 1 0 1 1 | 0 1 0 0 | 1 1 1 0 | 0 1 0 1 | 0 1 1 1 | 0

I want to be able to reduce this down to using only 6T CMOS.

I'm struggling to figure out how to reduce this from 9T down to 6T CMOS, and I'm not sure how to draw the CMOS transistor wiring diagram, schematic, the PDN & PUN with its connected output. I'm overlooking something, but I just can't seem to see it.

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    \$\begingroup\$ What is PDN and PUN \$\endgroup\$ Commented Feb 22 at 14:24
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    \$\begingroup\$ @SnappyRiffs Pull Down Network & Pull Up Network \$\endgroup\$ Commented Feb 22 at 16:19
  • \$\begingroup\$ I updated the truth table as for right now, it's exactly as it's supposed to be. \$\endgroup\$ Commented Feb 22 at 19:47

2 Answers 2

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First, correct the truth table.

If A, B, and C were high, then Y should be low.

After that, make K-Map to get the minimum SOP form.

$$Y = \overline{AC} + \overline{BC}$$

Use our imagination to get only the NAND or NOR gates with algebraic manipulation.

$$ \begin{align} Y & = \overline{C} \left(\overline{A}+\overline{B}\right) \\ & = \overline{C} \ \overline{(AB)} \\ \end{align} $$

It's just like NAND gate of (A,B) with active low enable pin of (C).

Or from another perspective it's just like NOR Gate with also active low enable pin.

$$ \begin{align} Y & = \overline{\overline{ \overline{C} \ \overline{(AB)} } } \\ & = \overline{ \overline{\overline{C}} + \overline{\overline{(AB)}} } \\ & = \overline{ C + (AB) } \end{align} $$

The original expression is actually already in minimal sum of product form except for the negation, so it's already straightforward to answer since transistors logics always have inversion, I just want to expand it generally.

CMOS NAND Gate with Enable

Falstad link.

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  • \$\begingroup\$ I did update the truth table sometime yesterday... It was missing a 1 output. I don't know why it's not there now. \$\endgroup\$ Commented Feb 22 at 19:32
  • \$\begingroup\$ I eventually worked it out several hours after I posted this. For the three inputs: It was simply A&B NOR C. I was struggling to translate it from the Logic to the NMOS implementation of it. \$\endgroup\$ Commented Feb 22 at 19:35
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    \$\begingroup\$ @FrancisCugler There was the suggested edit made on the question which I rejected since to me the edit appeared to correct the truth table entry for "A=1 B=1 C=1", but incorrectly changed the entry for "A=1 B=0 C=0". Two other reviewers approved the suggested edit which was then made, which probably explains your observation about "I don't know why it's not there now". \$\endgroup\$ Commented Feb 22 at 19:38
  • \$\begingroup\$ Nope the output is supposed to be 1 when they're all off, or only when A or B are high and nothing else. \$\endgroup\$ Commented Feb 22 at 19:40
  • \$\begingroup\$ If you look at the entire output top to bottom in a series making an 8bit word with the top being LSB and the bottom being MSB, the unsinged value should be 21. \$\endgroup\$ Commented Feb 22 at 19:52
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I was struggling to translate from the Boolean in terms of Logic Gates. I was easily able to use my Logic gates to get the functionality. It was when trying to implement it with transistors and reducing it from the 9T down to 6T that I was struggling with. Eventually, a few hours after I posted this, I ended up finding a working solution. Here's my implementation in Logisim:

Working Logisim Implementation

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