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I have a SystemVerilog module representing a 4-word x 3-bit ROM. It's from a textbook (Harris & Harris Digital Design and Computer Architecture), so I'm sure this isn't a typo. I understand that ROM is combinational only, and they use an always_comb statement and case statements, but then use nonblocking assignments. I'm trying to understand why.

module rom(input logic [1:0] adr, output logic [2:0] dout); always_comb case(adr) 2'b00: dout <= 3'b011; 2'b01: dout <= 3'b110; 2'b10: dout <= 3'b100; 2'b11: dout <= 3'b010; endcase endmodule
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    \$\begingroup\$ Being from a textbook does not necessarily mean it's typo-free. There can be surprisingly many mistakes in even well-respected textbooks. \$\endgroup\$ Commented Mar 24 at 0:47
  • \$\begingroup\$ One of the important matters to learn in academia is learning to doubt what the teachers, professors, textbooks, lecture materials etc. say. ;) \$\endgroup\$ Commented Mar 24 at 10:48

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While the syntax is legal, it does not follow the recommended good coding practices. It should use blocking assignments:

always_comb case (adr) 2'b00: dout = 3'b011; 2'b01: dout = 3'b110; 2'b10: dout = 3'b100; 2'b11: dout = 3'b010; endcase
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