The difference block with its two inputs tells you that you're looking at a feedback system, and it's clear where the feedback is coming from.
The integrator gives you high, theoretically infinite, gain at DC, so this feedback system is going to zero-out any DC difference between the DAC'd conversion of the output, and the input. This regardless of what components you include in the forward part of the loop.
If you don't put the D-latch in there, the loop will still operate to make the output similar to the input. It will self-oscillate (assuming some further delay in the loop, not shown explicitly) so that the average of the output is equal to the input. However, when it's done that, it's only of limited help to you. You could low-pass filter the output to recover a low-pass version of the input, that's what is going on with asynchronous PWM. You could use a counter to count how long the output has been high or low against some fast external clock, and process the output that way, some early high resolution ADCs worked like that.
What is more useful these days is to go directly to high speed binary samples. The D-latch aligns the transitions with a supplied clock, the clock now defining the times of our output samples. The closed loop adjusts its internal values so that the average of the output stream continues to track the average DC input.
Now we can use cheap, high speed digital filtering to recover the DC average of our input. This was not an option until relatively recently.
We can also increase the order of our loop, add more integrators (broken integrators to maintain stability), and increase the order of our output low pass digital filters, to get a noise-shaped delta sigma converter.
Although a one-bit DAC has no bit-to-bit alignment problems, its engineering is still not trivial if you want a high quality convertor. Note that the feedback loop is not driving the output samples to be equal to the input, it's driving the DAC-converted output samples to be equal to the input. This means that DAC must have no output non-linearity, with respect to its driving into different load voltages, or different data patterns. For instance, the data pattern 01100 has a different number of transitions to 01010. If TPHL is not equal to TPLH, those two patterns would have unequal DC analogue outputs, even though their digital DC value is the same.
