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I'm working on capturing ADC data from an ADA4355 using a Spartan-6 LX9 FPGA. According to the ADC datasheet, it can output data in several modes, such as:

16-Bit DDR/Single Data Rate (SDR), Two-Lane, 1× Frame Mode

Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode

I want to know the best way to capture this data correctly inside the Spartan-6, especially considering the ISERDES limitations (up to 8-bit deserialization per master/slave pair).

My main questions are:

  1. How should I configure the ISERDES (and possibly IDELAY or BUFIO/BUFR) blocks to handle the 16-bit DDR data correctly?

  2. Do I need to use multiple ISERDES blocks (e.g., master/slave configuration) for one data lane, and how should they be connected?

  3. Is there an example or reference design for a 16-bit DDR data capture from an ADC on Spartan-6?

  4. Between the “two-lane DDR” and “wordwise DDR one-lane” modes, which is more practical for a Spartan-6 implementation?

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  • \$\begingroup\$ I have done that for a similar ADC used in an infrared camera. IIRC, I used cascaded ISERDES to get the word length. I may have code that I can share, but it will take me a few days to dig through my archives -- busy weekend ahead! \$\endgroup\$ Commented Oct 18 at 14:04
  • \$\begingroup\$ Actually, now that I think about it, it was a matter of using two ISERDES in parallel for each lane, one clocked on the rising edge and one on the falling edge, and then interleaving the bits correctly on the output side. \$\endgroup\$ Commented Oct 18 at 14:11
  • \$\begingroup\$ Also, this work was done on an Artix-7. I haven't touched Spartan in quite a while, so I can't tell you how well this approach will map to that chip family. Hopefully, this will give you enough hints to get you on the right track. \$\endgroup\$ Commented Oct 18 at 23:08
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    \$\begingroup\$ @DaveTweed I finally got it working in Spartan-6 using the two-lane DDR mode with master+slave ISERDES pairs. Appreciate your insight! \$\endgroup\$ Commented Oct 19 at 11:29
  • \$\begingroup\$ I'm glad it was helpful! I'm still going to dig into my archives, if only to refresh my own memory. \$\endgroup\$ Commented Oct 19 at 18:13

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On Spartan-6, you can’t deserialize more than 8 bits per pin, so the practical way to capture the ADA4355’s 16-bit DDR output is to use the “two-lane, 1× frame, DDR” mode — not the single-lane 16-bit mode.

Each data lane (D0, D1) is handled by one ISERDES2 master + one ISERDES2 slave, giving you 8 bits per lane. You then combine the two lanes → 16-bit word.

Typical setup:

  • Each ADC LVDS pair → IBUFDS → ISERDES master/slave pair (DATA_WIDTH=8, DATA_RATE="DDR", BITSLIP_ENABLE="TRUE").

  • CLK0/CLK1 come from BUFPLL.IOCLK / inverted IOCLK.

  • CLKDIV comes from the ADC frame clock (FCO) routed through a BUFG.

  • IOCE connects to BUFPLL.SERDESSTROBE.

  • Register {lane1, lane0} on CLKDIV.

Why not single-lane 16-bit DDR? Because Spartan-6 ISERDES only supports 8-bit widths, a single-lane 16-bit would require capturing two frames and reassembling them in logic — much harder to align and less reliable.

So: I used two-lane DDR mode, one master+slave ISERDES per lane, BUFPLL-based clocking, and BITSLIP for alignment.

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