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I see multiple internal diagrams for the 555 timer IC. If I consider the following schematic, is the text below correct? (Also is this the correct diagram for the IC?)

555 timer

Author: EEGuide.com. Link: https://www.eeeguide.com/555-timer-circuit/

Looking at Q′ (the flip-flop complement):

  • Q′ = 0 → Final output high, capacitor charges
  • Q′ = 1 → Final output low, capacitor discharges

Looking at Q (direct flip-flop output), which controls the discharge transistor:

  • Q = 1 → transistor on → capacitor discharges → output low
  • Q = 0 → transistor off → capacitor charges → output high
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    \$\begingroup\$ To help get an answer by providing context, and to comply with the site rules for How to reference material written by others, please edit the question to include a link to the source of the diagram. \$\endgroup\$ Commented Nov 23 at 9:10
  • \$\begingroup\$ Deagle (nobody else), what capacitor do you refer to? \$\endgroup\$ Commented Nov 23 at 11:10
  • \$\begingroup\$ @Andyaka The timing capacitor \$\endgroup\$ Commented Nov 23 at 11:21

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There is a fine Wikipedia page for this IC. You can answer all the question from it.

Also is this the correct diagram for the IC?

It is functional equal.

If you compare it with the diagram of the Wikipedia page or, for example, with the TI data sheet, you will find that the flip-flop is commonly drawn with swapped set (S) and reset (R), and with an inverted output. The latter compensates the swap.

The meaning of correctness depends on the usage. It is fine to understand its function. But to map actual chips, it can be incorrect.

  • Q′ = 0 → Final output high, capacitor charges
  • Q′ = 1 → Final output low, capacitor discharges

As you don't define the circuit around the 555, we cannot check your conclusion about the capacitor. You can use the 555 for more then astable or monostable oscillators.

Assumed that you mean the common astable configuration, the relation between output and charge/discharge is correct. However, as your diagram shows a direct and non-inverted connection between Q' and output, your assignments are swapped.

  • Q = 1 → transistor on → capacitor discharges → output low
  • Q = 0 → transistor off → capacitor charges → output high

This is correct.

Compare it to your statements about Q': you cannot have the same result for Q = 1 and Q' = 1.

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  • \$\begingroup\$ Thank you for the help. So I'm assuming the below is correct? When Q = 1→ Transistor ON → capacitor discharges; Q′ = 0 → output LOW (Pin 3) When Q = 0→ Transistor OFF → capacitor charges; Q′ = 1 → output HIGH (Pin 3) \$\endgroup\$ Commented Nov 23 at 10:46
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    \$\begingroup\$ @Deagle Yes, that is correct. \$\endgroup\$ Commented Nov 23 at 12:39
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DISCH and OUT have the same logical state. The only difference between them is that DISCH is open-collector while OUT is push-pull.

Looking inside, transistor Qd is effectively an open-collector inverter. When the flop Q is high, Qd will be turned on, pulling DISCH low. Also, flop ~Q will be low, which makes OUT low.

DISCH is intended to discharge the timing capacitor when its voltage reaches 2/3 VCC. But that's not its only use. When making an astable (oscillator) it's sometimes better to use OUT as the feedback instead of DISCH so you can get better control of the duty cycle. This leaves DISCH available to do something else, like drive an LED or a fan PWM. Meanwhile, one-shots will still want to use DISCH for discharging.

More about the 555 here, including some nifty simulations: Is the NE555 the IC I need, and if not, what do I replace it with?

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