Questions tagged [sample-and-hold]
Anything related to sample and hold (S/H) circuits. S/H circuits are analog circuits whose purpose is that of sampling the instantaneous value of an analog signal and store that value for a predefined period of time. They are sort of analog memory circuits, and they are often employed as the first stage of analog to digital converter systems.
78 questions
-1 votes
2 answers
72 views
Buffer Reinforced Sample & Hold?
I have an application where I need to disconnect a node but maintain the analog value... Typically this is done with a sample and hold circuit with just a cap and a buffer... But I want / need to be ...
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2 votes
1 answer
84 views
Sample and hold (S&H) lower sample timing problem
I want to build a 1-octave keyboard and want to hold last note pressed. I hardly found some circuits online and they are working properly(ish) but when I press higher notes first and lower notes after,...
0 votes
1 answer
59 views
Sample and hold - high bandwidth signal, low bandwidth sample
I have an arbitrary waveform generator, the output of which occasionally 'glitches' while I am reprogramming the waveform to be applied - even for DC outputs. These glitches typically last of order ...
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1 vote
1 answer
64 views
Transient response of a sample and hold circuit
The above is a sample-and-hold circuit copied from here. I have this circuit designed in an IC, where Chold is about 3pF and the size of the MOS switch is 500nm/130nm. I observed a strange behaviour ...
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2 votes
1 answer
144 views
Conflicting Logic Thresholds in MAX4514 Datasheet for +12V Operation
I'm planning to use the MAX4514 with a +12V supply to reset integrator and sample-and-hold capacitors. In the "Logic-Level Thresholds" section, the datasheet states: The logic-level ...
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-1 votes
1 answer
117 views
Sample and hold with finite source impedance
Consider a voltage source connected to a single pole RC low pass filter. The output of the filter is connected to sampling circuit consisting of a switch and a capacitor. What is the sampled sequence ...
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1 vote
1 answer
57 views
Reg. LF398M S&H circuit not working
I'm trying to build a circuit which will hold the last value or pass the input when a logic signal toggles between 5V and 0V. LF398 IC seems to be a popular one, and I used this IC for the circuit. I ...
2 votes
1 answer
262 views
Is there a relation between sample & hold capacitor value and system clock speed?
Sometimes when looking at obscure and inadequate datasheets for various components I'll find an IC that has a pin for a sample & hold capacitor to connect to ground, but often times these ...
0 votes
2 answers
111 views
Sample/Hold Capacitor Not Holding As Expected
I'm working on a circuit to measure voltage across a shunt at 800ns and store it in a capacitor. Initially, the MOSFET switch is on, which allows the capacitor to track the input voltage from the ...
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0 votes
2 answers
88 views
Sample and Hold IC specification
I am currently designing my 3rd year project in EE. I have an MCU with an ADC that samples at 15 kHz. The signal I want to sample has a 0.5 µs rise time which is equivalent to a bandwidth of 700 kHz, ...
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0 votes
2 answers
286 views
Hold Step (pedestal) in a sample and hold circuit
I just read the Specifications and Architectures of Sample-and-Hold Amplifiers from TI as part of my studys for sample and hold circuits. On page three it says the following: Hold Step, also known as ...
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2 votes
2 answers
218 views
Best Practices for Preventing Oscillations When Interfacing an ADC with an OPA Output
I'm working on interfacing an ADC with the output of an operational amplifier. To mitigate signal integrity issues, my usual approach includes placing a small resistor near the OPA output and a small ...
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2 votes
1 answer
114 views
IC 74HC08 can the output drive the input without destroying it? [closed]
i made a circuit with a 74HC08 and i wanted that when the output is high(1Y) it would take over contact (1B) with a led between it .and the input B connected to ground with a 20K resistor it works ...
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3 votes
1 answer
170 views
How to reduce sample and hold circuit drift
I've built a sample and hold circuit on LTSpice, and the output will drift up at a rate of ~100mV/s. Is there an obvious way to reduce this? Is this a function of the FET / opamp used? The obvious ...
0 votes
2 answers
368 views
Resettable integrator resetting to the negative rail not ground
I've recently built a resettable integrator board which uses a low-drift JFET op-amp and a sample and hold chip. The sample and hold amplifier datasheet showed a resettable integrator configuration ...
