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Questions tagged [sequence-detector]

3 votes
2 answers
150 views

1. Problem Statement Design a synchronous Mealy finite-state machine that scans a continuous stream of letters (A, B, C, D) encoded in two bits and asserts y=1 only ...
Pato's user avatar
  • 1
2 votes
2 answers
162 views

I'm designing a finite state machine (FSM) that detects the sequences "01011" and "00101" in a serial binary input. When either sequence is detected, the FSM should output (Y1, Y2) ...
Turing's user avatar
  • 73
1 vote
1 answer
228 views

I was asked to design a Mealy FSM using SR Flip Flops to detect a pattern. It should detect if the pattern is either '1001' or '0110'. I was able to make the state diagram (I have attached the image), ...
Rach.1961's user avatar
1 vote
1 answer
235 views

This is the diagram, and the sequence we are detecting is 1011. The problem did not specify whether it is Mealy or Moore FSM, or whether it is overlapping or non-overlapping. When we get an input of ...
Obiick's user avatar
  • 189
2 votes
1 answer
3k views

I need to design a pattern detector that recognizes 100 and 111 bit patterns, even overlapping ones. I drew the state diagram as shown in the image and created the related table Could you tell me if ...
Vittorio Gatto's user avatar
0 votes
1 answer
735 views

I have an error in the form of HDL 9-806 on the begin statement. The code below is a button based sequence detector an addition LED flash when sequence is correct with a debouncer to stop multiple ...
S G's user avatar
  • 1
4 votes
2 answers
2k views

I am designing "0110" overlapping sequence detector using Moore FSM model in Verilog. ...
user299749's user avatar
2 votes
1 answer
416 views

The code I am using is the following. I am using five states as this is a Moore model, and non-overlapping sequence is assumed. The state logic is correct as far as I can tell. However, when I run it, ...
Mehar's user avatar
  • 21

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