• I'm tring to integrate a SPI Slave in VHDL (opencores) http://opencores.org/project,spi_master_slave
• the idea is to interface a Microcontroller and an FPGA
• I'm Using Quartus..

more info:

• microcontroller diferent clock 50 MHz i think..

• SPI clock frequency is 16Mhz

• SPI VHDL core clock @ 100 Mhz

• I've made an endurance test writing and reading some registers .. no errors with spi

the problem :

• when I try to integrate the VHDL SPI to the rest of my VHDL application (also 100mhz)... the circuit becomes a little "unstable"

some symptoms:

• sometimes in some registers there are bits I didnt write by spi, making the vhdl application to act inexpectecly..

• When adding signaltap probes , the behabior of the vhdl changes a little..

questions:

Do I need to use timequest for the SPI CORE , to add timeconstraingts to SPI input pins? Do I have metastability ?