Questions tagged [quartus]
Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).
364 questions
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How to test LVDS output clock on DE2-115 using ALTLVDS_TX Megafunction?
I’m trying to test the LVDS output on my Altera DE2-115 board using Quartus Prime 18.1 Lite. My goal is just to generate and output a clock signal over an LVDS pair using the ALTLVDS_TX Megafunction. ...
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1 vote
1 answer
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Why is the waveform not matching? (2 clock delay in FSM code)
Context : I have been tasked with testing a HC-04 Ultrasonic sensor with Verilog, and below is the Verilog code, the testbench and the waveform that I am getting, ...
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1 vote
1 answer
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What to do when a Verilog state machine simulation doesn't reflect the signals?
I'm working on a Verilog project using ModelSim, and I've created a testbench to simulate the behavior of a module called Elevator_FSM, which models an elevator's operation. My goal is to assign ...
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-1 votes
1 answer
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How to open the precompiled Quartus Prime project
I have precompiled (with db and incremental_db folders, so it have sof/pof files) Quartus Prime (22.1std.1 Build 917 02/14/2023 SC Lite Edition) project and want to open "Technology Map Viewer (...
- 363
1 vote
0 answers
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SDRAM to OCM via DMA on the Agilex 5
I am in the process of learning about communication between SDRAM and OCM via DMA, using the Agilex-5. The idea will be to write 0xdeafbeef to the SDRAM, then ...
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1 vote
1 answer
61 views
How to properly connect a circuit with a feedback loop in Quartus schematic editor
I'm trying to implement the circuit in the picture above. However every time I compile Quartus tells me I can't assign two values to the output pin. Is there a way to tell Quartus that the bottom wire ...
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0 votes
1 answer
93 views
How to specify clock period in Synopsys Design Constraints file (SDC)?
The SDC file: create_clock –period 37 –waveform {0 18.519} {clk} While reading SDC file in the Quartus, I get following error: ...
- 363
1 vote
2 answers
224 views
Reaction on signal changing using always block in Verilog not work after FPGA programming
I want to do synthesizable always block, that would execute code by d1 signal changing (posedge and ...
- 363
1 vote
2 answers
153 views
Cast Verilog 16-bit expressions to 8 bits
How do I cast from 16 bits to 8 bits? ... output [ 7:0] audioData ); bit [15:0] audioSum; // Get the 8-bit output assign audioData = (audioSum >> 1); I ...
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-1 votes
1 answer
190 views
Quartus reporting less processors in system than actual available number
I'm new to FPGA and I'm starting to learn it with Quartus Prime Lite 23.1std. After seeing the warning ...
4 votes
3 answers
1k views
How to connect three 7-segment displays to a 4x4 binary multiplier
I am trying to connect three 7-segment displays to show the result. I thought about using the IC 7448 (I could also use the 7447), but I assigned 4 outputs to each encoder (first issue, as I need 3 ...
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1 answer
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Preset logic for Flip-Flop down counters. How can I preset the initial value until the count starts?
I'm trying to design a 59 second countdown on Quartus Prime, using a 4-bit JK stage for the second units and a 3-bit JK stage for the second tens. However, I've run into what I feel is a simple ...
0 votes
1 answer
174 views
Decrease system clock frequency in Quartus II?
How to decrease system clock frequency in Quartus II from standard 50 MHz to 2 Hz (two clock fronts per second)? I find out it easier using constraints editing way, namely, SDC (Synopsys Design ...
- 363
-1 votes
1 answer
123 views
Found illegal assignment group name conflicts with top-level node name
How to fix the follow errors was appeared after pin assingment (in Pin Planner window) and project compilation: "Error: Found illegal assignment group name "key" -- conflicts with top-...
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1 vote
1 answer
426 views
Making memory in FPGA and how to use the SDRAM on De1-Soc board
Im working in a project with A FPGA board (De1-Soc - Cyclone V) and in project there is supposed to be an internal memory to make connection with rest of the system and read or write some data in it. ...
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