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  1. OpenSERDES OpenSERDES Public

    Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

    Verilog 258 45

  2. X-DeepSCA X-DeepSCA Public

    Power side-channel traces from the Atmega microcontroller and the codes for cross-device deep learning side-channel attack (X-DeepSCA)

    Python 8 1

  3. Sparclab-RF-PUF-Dataset Sparclab-RF-PUF-Dataset Public

    A dataset containing 30 Xbee S2C transmitter data for both including and excluding wireless channel

    4

  4. Syn-STELLAR Syn-STELLAR Public

    Verilog 2

  5. CS-Audio CS-Audio Public

    Test inputs to CS-Audio and recovered audio files

  6. SCNIFFER SCNIFFER Public