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clock-domain-crossing

Here are 10 public repositories matching this topic...

hdl-modules

hdl-modules / hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

asic fpga hardware amd vhdl intel eda rtl ip xilinx vivado altera fifo cdc axi microsemi clock-domain-crossing asynchronous-fifo axi-lite efinix

Updated Nov 24, 2025
VHDL

akhan3 / async-fifo

Asynchronous FIFO for transferring data between two asynchronous clock domains

fpga fifo clock-domain-crossing

Updated Jun 3, 2016
Verilog

AngeloJacobo / FPGA_Asynchronous_FIFO

FIFO implementation with different clock domains for read and write.

fpga asynchronous verilog fifo clock-domain-crossing

Updated Aug 17, 2021
Verilog

hdl-util / clock-domain-crossing

Utilities for clock-domain crossing with an FPGA

fpga verilog systemverilog clock-synchronization clock-domain-crossing clock-domains

Updated Jun 27, 2020
SystemVerilog

takatz28 / FIFO-BIST

Final project for the class "Application Specific Integrated Circuit Development"

systemverilog fifo clock-domain-crossing built-in-self-test

Updated Oct 21, 2021
SystemVerilog

w-tr / clock-domain-crossing

In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.

synchronization clock cdc clock-design clock-synchronization clock-domain-crossing clock-domains

Updated Nov 20, 2020
VHDL

egk696 / InterChip_Bridge

A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs

fpga communication-protocol asynchronous embedded-systems fault-tolerant fault-detection network-on-chip interchip-bridge clock-domain-crossing

Updated Oct 30, 2017
VHDL

VLSI-Shubh / Asynchronous-FIFO

Production-ready asynchronous FIFO buffer with independent read/write clock domains for safe CDC operations. Features Gray code pointers, dual flip-flop synchronizers, metastability prevention, and parameterized design. Essential for SoC inter-module communication and multi-clock systems.

verilog metastability gray-code clock-domain-crossing vlsi-design soc-design

Updated Nov 28, 2025
Verilog

AbhijeetJ-512 / FIFO

RTL designs and simulations for FIFO buffers (Synchronous & Asynchronous) in Verilog, targeting robust data handling architectures.

fsm fifo clock-domain-crossing gray-code-usage

Updated May 18, 2025
Verilog

dianluniuniu / async-fifo

Parameterizable Asynchronous FIFO with Gray Code Synchronization - A robust clock domain crossing solution in SystemVerilog

asic fpga verilog systemverilog fifo digital-design gray-code clock-domain-crossing asynchronous-fifo rtl-design

Updated Nov 20, 2025
SystemVerilog

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