A systemVerilog implementation of the Game Boy on DE1-SoC
This was for CSEE 4840 Embedded System Design @ Columbia University
To make target files for DE1-SoC make qsys && make quartus && make rbf
Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours cpu instrs 👍 👍 👍 👍 👍 👍 👍 dmg sound ❌ 👍 N/A N/A N/A N/A ❌ instr timing 👍 👍 N/A N/A N/A N/A 👍 interrupt time N/A ❌ N/A N/A N/A N/A ❌ mem timing N/A 👍 N/A N/A N/A N/A 👍 mem timing 2 👍 👍 N/A N/A N/A N/A 👍 oam bug ❌ ❌ N/A N/A N/A N/A ❌
Mooneye GB acceptance tests Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours add sp e timing 👍 ❌ 👍 👍 👍 👍 👍 call timing 👍 ❌ 👍 👍 👍 👍 👍 call timing2 👍 ❌ 👍 👍 👍 👍 👍 call cc_timing 👍 ❌ 👍 👍 👍 👍 👍 call cc_timing2 👍 ❌ 👍 👍 👍 👍 👍 di timing GS 👍 👍 👍 👍 👍 👍 👍 div timing 👍 👍 👍 👍 👍 👍 👍 ei sequence 👍 👍 👍 👍 ❌ 👍 👍 ei timing 👍 👍 👍 👍 👍 👍 👍 halt ime0 ei 👍 👍 👍 👍 👍 👍 👍 halt ime0 nointr_timing 👍 👍 👍 👍 👍 ❌ 👍 halt ime1 timing 👍 👍 👍 👍 👍 👍 👍 halt ime1 timing2 GS 👍 👍 👍 👍 👍 ❌ 👍 if ie registers 👍 👍 👍 👍 👍 ❌ 👍 intr timing 👍 👍 👍 👍 👍 ❌ 👍 jp timing 👍 ❌ 👍 👍 👍 👍 👍 jp cc timing 👍 ❌ 👍 👍 👍 👍 👍 ld hl sp e timing 👍 ❌ 👍 👍 👍 👍 👍 oam dma_restart 👍 ❌ 👍 👍 👍 👍 ❌ oam dma start 👍 ❌ 👍 👍 👍 👍 👍 oam dma timing 👍 ❌ 👍 👍 👍 👍 ❌ pop timing 👍 ❌ 👍 👍 👍 👍 👍 push timing 👍 ❌ ❌ 👍 👍 👍 👍 rapid di ei 👍 👍 👍 👍 👍 👍 👍 ret timing 👍 ❌ 👍 👍 👍 👍 👍 ret cc timing 👍 ❌ 👍 👍 👍 👍 👍 reti timing 👍 ❌ 👍 👍 👍 👍 👍 reti intr timing 👍 👍 👍 👍 👍 👍 👍 rst timing 👍 ❌ ❌ 👍 👍 👍 👍
Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours daa 👍 👍 👍 👍 👍 👍 👍
Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours ie push 👍 ❌ ❌ ❌ ❌ 👍 👍
Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours basic 👍 👍 👍 👍 👍 👍 👍 reg_read 👍 👍 👍 ❌ ❌ 👍 👍 sources dmgABCmgbS 👍 👍 ❌ ❌ ❌ ❌ 👍
Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours boot sclk align dmgABCmgb ❌ 👍 👍 ❌ ❌ 👍 👍
Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours hblank ly scx timing GS 👍 👍 ❌ ❌ 👍 ❌ ❌ intr 1 2 timing GS 👍 👍 👍 👍 👍 ❌ ❌ intr 2 0 timing 👍 👍 ❌ 👍 👍 ❌ ❌ intr 2 mode0 timing 👍 👍 ❌ ❌ 👍 ❌ 👍 intr 2 mode3 timing 👍 👍 ❌ ❌ 👍 ❌ 👍 intr 2 oam ok timing 👍 👍 ❌ ❌ 👍 ❌ 👍 intr 2 mode0 timing sprites ❌ 👍 ❌ ❌ 👍 ❌ ❌ lcdon timing dmgABCmgbS ❌ 👍 ❌ ❌ ❌ ❌ ❌ lcdon write timing GS ❌ 👍 ❌ ❌ ❌ ❌ ❌ stat irq blocking ❌ 👍 👍 ❌ 👍 ❌ 👍 stat lyc onoff ❌ 👍 ❌ ❌ ❌ ❌ ❌ vblank stat intr GS 👍 👍 ❌ 👍 👍 ❌ 👍
Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours div write 👍 👍 ❌ 👍 👍 👍 👍 rapid toggle 👍 👍 ❌ ❌ 👍 👍 👍 tim00 div trigger 👍 👍 👍 ❌ 👍 👍 👍 tim00 👍 👍 ❌ 👍 👍 👍 👍 tim01 div trigger 👍 👍 ❌ ❌ 👍 👍 👍 tim01 👍 👍 👍 👍 👍 👍 👍 tim10 div trigger 👍 👍 ❌ ❌ 👍 👍 👍 tim10 👍 👍 ❌ 👍 👍 👍 👍 tim11 div trigger 👍 👍 ❌ ❌ 👍 👍 👍 tim11 👍 👍 ❌ 👍 👍 👍 👍 tima reload 👍 👍 ❌ ❌ 👍 👍 👍 tima write reloading 👍 👍 ❌ ❌ 👍 👍 👍 tma write reloading 👍 👍 ❌ ❌ 👍 👍 👍
Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours MBC1 N/A 👍 N/A N/A N/A N/A 👍 MBC5 N/A 👍 N/A N/A N/A N/A 👍
Note: MBC3 test ROM was not created at the time of testing.
