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Pull requests: llvm/llvm-project
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[RISCV] Sources of vmerge shouldn't overlap V0 backend:RISC-V llvm:globalisel
#170070 opened Dec 1, 2025 by wangpc-pp Loading…
[SelectionDAG] Add SelectionDAG::getTypeSize. NFC backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#169764 opened Nov 27, 2025 by lukel97 Loading…
[RISCV] LMUL lists for indexed and strided loads backend:RISC-V
#169756 opened Nov 27, 2025 by ppenzin Loading…
[RISCV] Rename SFB Base Feature backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#169607 opened Nov 26, 2025 by lenary Loading…
[RISCV] Only convert volatile i64 load/store to Zilsd in SelectionDAG. backend:RISC-V
#169529 opened Nov 25, 2025 by topperc Loading…
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading…
[RISCV] Introduce a new tune feature string syntax and its parser backend:RISC-V tablegen
#168160 opened Nov 15, 2025 by mshockwave Loading…
DAG: Use poison for some load/store offsets in legalizer backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#167756 opened Nov 12, 2025 by arsenm Loading…
[RISCV][llvm-objdump] Support --symbolize-operands backend:RISC-V llvm:binary-utilities
#166656 opened Nov 5, 2025 by lenary Loading…
[lldb][RISCV] Implement trap handler unwind plan backend:RISC-V lldb
#166531 opened Nov 5, 2025 by sga-sc Loading…
[VPlan] Narrow VPWidenCastRecipe to scalar cast recipe. backend:RISC-V llvm:transforms vectorizers
#166514 opened Nov 5, 2025 by Mel-Chen Loading…
[RISCV][GISel] Legalize the G_FCANONICALIZE instruction backend:RISC-V llvm:globalisel
#166162 opened Nov 3, 2025 by circYuan Loading…
Refactor WIDE_READ to allow finer control over high-performance function selection backend:RISC-V bazel "Peripheral" support tier build system: utils/bazel libc
#165613 opened Oct 29, 2025 by Sterling-Augustine Loading…
[VPlan] Replace ExtractLast(Elem|LanePerPart) with ExtractLast(Lane/Part) backend:RISC-V llvm:transforms vectorizers
#164124 opened Oct 18, 2025 by fhahn Loading…
[RISCV] Remove experimental from Zicfilp and Zicfiss backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#157015 opened Sep 5, 2025 by tclin914 Loading…
[clang][RISCV][Zicfilp] Force user to use Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
-mcf-branch-label-scheme=unlabeled backend:RISC-V clang:frontend #152122 opened Aug 5, 2025 by mylai-mtk Loading…
[CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction backend:AArch64 backend:AMDGPU backend:ARM backend:RISC-V llvm:codegen llvm:globalisel llvm:mc Machine (object) code llvm:support mlgo
#151944 opened Aug 4, 2025 by vg0204 Loading…
[RISCV] custom scmp(x,0) and scmp(0,x) lowering for RVV backend:RISC-V
#151753 opened Aug 1, 2025 by camel-cdr Loading…
[RISCV] Put Large Code Model Constant Pools in .text backend:Lanai backend:MIPS backend:NVPTX backend:RISC-V backend:SPIR-V backend:X86 llvm:codegen
#151393 opened Jul 30, 2025 by lenary Loading…
[RISCV] Prefer preindexed addressing mode when XTheadMemIdx exists backend:RISC-V llvm:transforms
#147921 opened Jul 10, 2025 by wangpc-pp Loading…
[LangRef] Require that vscale be a power of two backend:AArch64 backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:transforms vectorizers
#145098 opened Jun 20, 2025 by preames Loading…
[RISCV] Allocate feature bits for Zifencei and Zmmul backend:RISC-V compiler-rt:builtins compiler-rt
#143306 opened Jun 8, 2025 by Wren6991 Loading…
[RISCV] Add basic Mach-O triple support. backend:RISC-V llvm:binary-utilities llvm:mc Machine (object) code
#141682 opened May 27, 2025 by fpetrogalli Loading…
[VPlan] Use VPInstructionWithType for uniform casts. backend:RISC-V llvm:transforms vectorizers
#140623 opened May 19, 2025 by fhahn Loading…
[RISCV][MC] Add aliases for beq/bne with x0 as the first argument => beqz/bnez backend:RISC-V llvm:mc Machine (object) code
#139086 opened May 8, 2025 by asb Loading…
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