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Pull requests: llvm/llvm-project
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Avoid maxnum(sNaN, x) optimizations / folds backend:AMDGPU backend:ARM backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:SelectionDAG SelectionDAGISel as well llvm:transforms
#170181 opened Dec 1, 2025 by LewisCrawford Loading…
[X86] Lower
minimum/maximum/minimumnum/maximumnum using bitwise operations backend:X86 #170069 opened Dec 1, 2025 by valadaptive Loading…
[X86][GlobalISel] Support globals in pic mode backend:X86 llvm:globalisel llvm:support mlgo
#170038 opened Nov 30, 2025 by e-kud Loading…
[RegisterCoalescer] The COPY with the implicit-def of super register is not coalescable. backend:X86 llvm:codegen llvm:regalloc
#169997 opened Nov 29, 2025 by dianqk Loading…
[X86] optimize saturating (masked) pack backend:X86
#169995 opened Nov 29, 2025 by folkertdev Loading…
[X86][Clang] Support constexpr evaluation of cvtpd2ps intrinsics backend:X86 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category
#169980 opened Nov 29, 2025 by HamzaHassanain Loading…
[X86][GlobalISel] Set Dst register correctly when narrowing G_ICMP backend:X86 llvm:globalisel
#169947 opened Nov 28, 2025 by e-kud Loading…
[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding
#169885 opened Nov 28, 2025 by arcbbb Loading…
[Codegen][NewPM] Explicitly Nest Passes in CodegenPassBuilder backend:AMDGPU backend:X86
#169867 opened Nov 28, 2025 by boomanaiden154 Loading…
[X86] optimize masked truncated saturating stores backend:X86
#169827 opened Nov 27, 2025 by folkertdev Loading…
[X86] Add ISD::MULHS/MULHU v4i64/v8i64 lowering backend:X86 llvm:SelectionDAG SelectionDAGISel as well
[DAG] Recognise AVGFLOOR (((A >> 1) + (B >> 1)) + (A & B & 1)) patterns backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#169644 opened Nov 26, 2025 by RKSimon Loading…
[x86][AVX-VNNI] Fix VPDPWXXD Argument Types backend:X86 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics compiler-rt:sanitizer llvm:ir llvm:transforms
#169456 opened Nov 25, 2025 by BaiXilin Loading…
[Clang][X86] Add tests for AVX512 integer comparison intrinsics to be used in constexpr backend:X86 clang Clang issues not falling into any other category
#169452 opened Nov 25, 2025 by shri-acha Loading…
optimize SelectionDAGISel as well
is_finite assembly backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG #169402 opened Nov 24, 2025 by folkertdev Loading…
X86: make VBMI2 funnel shifts use VSHLD/VSHRD for const splats backend:X86
#169401 opened Nov 24, 2025 by ArnavM3434 Loading…
[SPIR-V] [HLSL] Add CheckAccessFullyMapped HLSL function. backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics HLSL HLSL Language Support llvm:ir
[Clang][x86]: allow PCLMULQDQ intrinsics to be used in constexpr backend:X86 clang:bytecode Issues for the clang bytecode constexpr interpreter clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#169214 opened Nov 23, 2025 by ahmednoursphinx Loading…
[X86] Remove redundant TEST after shifts when count is non-zero backend:X86 llvm:codegen llvm:SelectionDAG SelectionDAGISel as well
#169069 opened Nov 21, 2025 by GrumpyPigSkin Loading…
[RegisterCoalescer] Don't commute two-address instructions which only define a subregister backend:SystemZ backend:X86 llvm:codegen llvm:regalloc
#169031 opened Nov 21, 2025 by KRM7 Loading…
x86: fix musttail sibcall miscompilation backend:X86
#168956 opened Nov 20, 2025 by folkertdev Loading…
[HLSL] Implement ddx and ddy HLSL intrinsics backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics HLSL HLSL Language Support llvm:ir
#168887 opened Nov 20, 2025 by Alexander-Johnston Loading…
[HLSL] Implement ddx/ddy_fine intrinsics backend:DirectX backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics HLSL HLSL Language Support llvm:ir
#168874 opened Nov 20, 2025 by Alexander-Johnston Loading…
[SelectionDAG] Add TRUNCATE_SSAT_S/U and TRUNCATE_USAT_U to canCreateUndefOrPoison and computeKnownBits (#152143) backend:AArch64 backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#168809 opened Nov 20, 2025 by kuroyukiasuna Loading…
[CIR][X86] Add support for kunpck builtins backend:X86 clang Clang issues not falling into any other category ClangIR Anything related to the ClangIR project
#168757 opened Nov 19, 2025 by ahmednoursphinx Loading…
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