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1. mips-pipeline-sv mips-pipeline-sv Public

   Work-in-progress RTL pipelined MIPS processor in SystemVerilog, targeting FPGA deployment on DE10-Lite.

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2. MIPS_Assembler MIPS_Assembler Public

   Python based assembler that converts .asm files into two hex files, one for instruction memory and one for data memory. Used in combination with DE-10 lite MIPS implementation.

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3. lab6 lab6 Public

   for lab 6

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4. VGA-FrameBuffer-Car VGA-FrameBuffer-Car Public

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5. first-contributions first-contributions Public

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   🚀✨ Help beginners to contribute to open source projects

6. NotepadNext NotepadNext Public

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   A cross-platform, reimplementation of Notepad++

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