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BitBake 2 4 Updated Dec 12, 2024

Links to the RVfpga materials developed by Imagination Technologies, and recent additions on teaching materials and experiences, papers, talks, and tools.

C 28 2 Updated Mar 19, 2026

Minimal SoC containing a Serv-RV32I Core designed for usage with Liberty74

Verilog 3 Updated Jun 2, 2024

An abstraction library for interfacing EDA tools

Python 756 223 Updated Mar 11, 2026

Small SERV-based SoC primarily for OpenMPW tapeout

Verilog 51 12 Updated Dec 18, 2025

Package manager and build abstraction tool for FPGA/ASIC development

Python 1,398 269 Updated Feb 13, 2026

SERV - The SErial RISC-V CPU

Verilog 1,768 249 Updated Feb 19, 2026

A collection of core generators to use with FuseSoC

Python 18 13 Updated Aug 23, 2024

FuseSoC standard core library

158 42 Updated Mar 11, 2026

Example LED blinking project for your FPGA dev board of choice

Tcl 191 79 Updated Feb 28, 2026

FOSSi Foundation Website

HTML 1 Updated Mar 19, 2020

FuseSoC-based SoC for VeeR EH1 and EL2

Verilog 338 73 Updated Dec 11, 2024

mor1kx - an OpenRISC 1000 processor IP core

Verilog 578 154 Updated Aug 21, 2025
Python 1 Updated Aug 19, 2016