VeeR EH1 core
fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer
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May 29, 2023 - SystemVerilog
#
fusesoc
Here are 28 public repositories matching this topic...
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2
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Mar 12, 2026 - SystemVerilog
Example of how to get started with olofk/fusesoc.
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Jul 25, 2021 - Python
A quick SPI BFM to assist in SPI device testing and development
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Jan 15, 2024 - SystemVerilog
Just a set of Dockerfiles and tools for FuseSoC
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Nov 12, 2018 - Dockerfile
A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
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Aug 2, 2023 - Makefile
Find first set operation in Verilog-2001 with logarithmic complexity.
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Nov 1, 2021 - Verilog
A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.
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Oct 23, 2022 - Verilog
NES Controller Interface written in Verilog-2005
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Mar 18, 2024 - Verilog
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