Must-have verilog systemverilog modules
spi-interface fpga hls encoder delay tcl verilog debounce xilinx synchronizer uart altera uart-verilog fifo pwm uart-protocol spi-master uart-controller uart-tx uart-receiver
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Aug 2, 2025 - Verilog
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uart-protocol
Here are 23 public repositories matching this topic...
Interface Protocol in Verilog
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Aug 2, 2019 - Verilog
Basic UART TX/RX module for FPGA
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Oct 18, 2018 - Verilog
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
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Apr 29, 2023 - Verilog
UART - RTL Design and Verification
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Sep 6, 2021 - Verilog
☎️ UART Communication Implementation in Verilog HDL
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Mar 22, 2022 - Verilog
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Mar 16, 2019 - Verilog
Verilog Modeling of UART Tx and Rx
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May 5, 2020 - Verilog
Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate th…
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May 18, 2021 - Verilog
Transferring data from SPI to UART using BMP280 sensor with Verilog
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Oct 5, 2024 - Verilog
Verilog implementation of APB bus using VAAMAN.
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Dec 30, 2023 - Verilog
📌 The idea of this project is to build a system that uses the existing lights to detect the location of a user within an indoor environment. For this, we can use Visible Light Communication (VLC) technology. The basic concept is to have four LEDs transmitting their IDs one after the other at fixed intervals.
c-sharp arduino fpga intel visible-light-communication uart-protocol serial-communication altera-fpga
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Apr 27, 2023 - Verilog
This repository contains the Verilog implementation of a UART protocol with FIFOs for handling data transmission and reception.
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Aug 10, 2025 - Verilog
UART implementation using Verilog HDL
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Jan 23, 2022 - Verilog
300 baud 8N1 UART transmitter with limited character set (0x40..0x5F) loading as ASIC design
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Sep 30, 2022 - Verilog
Final project for Digital Systems, IITGN Spring '25
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Aug 30, 2025 - Verilog
verilog-uart
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Jul 7, 2024 - Verilog
En el presente repositorio se encuentra toda la documentacion del proyecto general y de cada grupo de trabajo, para cada instrumento hay una carpeta destinada que contiene toda la descripcion del proceso de desarrollo, tanto a nivel de software como a nivel de hardware. Todos contaron con la tutoria del Ingeniero Electronico Johnny Cubides.
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Jul 24, 2025 - Verilog
🔐 UART compatible hardware based FPGA encryption device
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Dec 24, 2020 - Verilog
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