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Note: Just tell me if my reasoning or logic is wrong.

So I have two numbers 01001 and 1110. And the question asks to subtract them as both signed and unsigned system.

Unsigned System

For this I can use, subtraction via addition (2's compliment system).

Question: 01001 - 1110 1110 -> 01110 // Sign extension 01110 -> 10001 // Inverting Bits 10001 + 1 -> 10010 // Adding one Now, 01001 10010 + ----- 11011

From my book it says, "No final carry in step 2 indicates a final borrow, or a greater “2nd number” than the “1st number”, hence an impossible subtraction." So I concluded Overflow generated and borrow occurred as the second number is greater than first number.

Signed System

Question: 01001 - 1110 1110 -> 11110 // Sign extension Now, Carry:1 1 000 0 1001 1 1110 + ------- 0 0111

The book says, "In 2’s complement subtraction modeled by Equation (7), and also in 2’s complement addition, overflow occurs if and only if the carry bit arriving at the sign column is different from the carry bit leaving this column." Hence, No overflow and borrow occurred.

Is there anything I left or didn't consider? For some reason I feel like I messed up signed part even though the result makes sense. 9 -2 = 7

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Lets say the question is 01001 - 1110

Now we have two options. Calculate is using Unsigned System and then do it using signed system.

Unsigned System

01001 is five bits while 1110 is four bytes.

The first step is to sign extend and make sure they both are of equal length. For unsigned, we sign extend by adding "0s" on left most side. Hence,

1110 -> 01110

Now the subtraction. In term of decimal the question looks like this: 9-14. Which is -5

// Taking 2s compliment of 01110 01110 -> 10001 // Inverting Bits 10001 + 1 -> 10010 // Adding one Now, 01001 // 9 10010 // -14 + ----- 11011 // -5 if we consider it signed system, otherwise 27

"No final carry in step 2 indicates a final borrow, or a greater “2nd number” than the “1st number”, hence an impossible subtraction." In unsigned, -5 can't be represented anyways. Hence Overflow occured.

Signed System

For signed System the procedure is more or less the same. The major difference would be the sign extension.

For signed numbers, to do signed extension, we just repeat whatever the MSB is. For 1110, MSB is 1 Hence,

1110 -> 11110

Now the subtraction. In term of decimal the question looks like this: 9-(-2). Which is 11.

// Taking 2s compliment of 01110 11110 -> 00001 // Inverting Bits 00001 + 1 -> 00010 // Adding one Now, 01001 // 9 00010 // -2 - ----- 01011 // 11, as expected

Since the carry bit arriving arriving at the sign column is same from the carry bit leaving this column. We have no overflow.

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