From what I read, VLIWs execute instructions in bundles, i.e. the CPU loads a bundle of instructions and dispatches them all at once. This is possible because the compiler scheduled instructions in such a way that there are no data dependencies between instructions in a single bundle (on a superscalar architecture instructions to be executed concurrently are scheduled dynamically by the CPU).
Now, suppose that one of the operations in a bundle throws an exception, e.g. a divide by zero, or a read from empty register. This is easy to reason about and can be handled without much effort - the CPU switches to a sequential execution model, services the exception, switches back to normal operation mode and continues execution as if nothing happened.
Example 1: one exception in a single bundle
; pseudo-asm code ; assume, two-instruction bundles loadint r1,#0 loadint r2,#2 ; raises "divide by zero" divideint r3,r2,r1 nop My question is - what happens when two (or possibly more) instructions in a single bundle raises an exception? How does the CPU handle that? One idea I got is that the CPU can store the actual dispatch order of instructions and handle all exceptions in the same order as the instructions that raised them were dispatched, and then continue.
Example two: two exceptions in a single bundle
; pseudo-asm code ; assume, two-instruction bundles loadint r1,#0 loadint r2,#2 ; raises "divide by zero" divideint r3,r2,r1 ; raises "read from empty register (r4)" addint r5,r3,r4 The literature I found discusses only the one-active-exception case, or deals with other aspects of exception handling (for example, performance).
