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I am researching the Waveshare High-Precision AD/DA Board. Why does this board use GPIO pins as "Chip Select" pins?

My understanding is that an SPI bus typically uses one of two "CE" pins for chip select. But the Waveshare board apparently uses GPIO. What might be the reasoning for this? And does this mean that the CEx pins are not used (i.e. not connected to either of the converter chips) at all?

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  • What do you think the "CE" pins are if not GPIO pins that were dedicated to being connected to some chips' enable pins? Commented Nov 17, 2017 at 20:40

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Looking at the schematic of the AD/DA board you referenced, the CS0 and CS1 pins are directly connected to the AD and DA CE pins. If I were designing the board, I would have over-engineered it and placed a 2 to 4 decoder and a bus controller... which would be too many chips... and my boss would ask me to cut back the components.

The AD only "sends" data and the DA only "receives" data. So, the CS pins allow independent selection of whether the SPI bus is, to borrow GPIB terminology, a "listener" or a "talker" or both.

To more directly answer the question...

The DAC8532 on the board is not an SPI device. It accepts serial input into its shift register as can be seen on its datasheet However, it's not strictly SPI. The device is not tolerant of SPI protocols.

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  • So does that mean that P_CE0 and P_CE1 do nothing? Commented Nov 17, 2017 at 19:38
  • @eczajk: Those pins are not connected, so they don't apply to this board. Commented Nov 17, 2017 at 20:36
  • This is a 30 year old DAC design from Burr-Brown hence the awkward serial protocol. Commented Nov 18, 2017 at 4:38

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