- DRAM memory is accessed in rows and columns with a multiplexed address bus with row and column addresses sent separately. The DRAM chips used, e.g. TI 4116, were organized as 16384 addresses of 1-bit storage, and the 14-bit address is sent as 7-bit row and 7-bit columns.
As DRAMs store data bits as small charge into a tiny capacitor, the charge leaks and originally stored bit becomes unreadable unless the storage cell is periodically updated by reading back what is stored there and writing it again to prevent the bit from corrupting. This is called the refresh cycle and those DRAM chips used had a refresh requirement of updating each row every 2ms, and since the row address is 7-bit, there are 128 rows, and refreshing each row updates all the 128 column bits.
The Z80 CPU has a built-in feature to support refreshing DRAM memory, by keeping a 7-bit refresh counter in the register R. The refresh counter is increased by 1 after every instruction opcode fetch, and after the instruction opcode has been fetched and being decoded, the idle time on the bus is used to do a refresh bus cycle with the register R contents being sent out as the address. This refresh bus cycle can be used as DRAM refresh cycle with the 7-bit row address coming from the R register so a row is updated after each opcode fetch. This was very typical in Z80 machines in the era, including the ZX Spectrum.
The simplified version is, the R register is typically directly used as the DRAM row address for refresh.
I accidentally explained this already in #1, but to a DRAM memory, in addition to actually reading or writing data, the refresh cycle internally reads a row of bits and writes them back to keep the stored bits from fading away and getting corrupted.
As the R register is writable and readable, and 7 lowest bits are automatically inceremented for every refresh cycle, you can do anything you want with it, provided that it does not prevent refreshing the memory properly.
The refresh feature has reportedly been used used as simple DMA engine to e.g. copy data from SRAM to a LCD screen. As SRAMs don't need the refresh cycle, it can be used to read SRAM and write it to somewhere like a LCD display. The R register contents and thus the row address may or may not be used by the hardware. It might be useful for any other data-shoveling purposes that does not require a specific timing and can work with irregular timing.
It can be used for pseudo-random numbers quite easily as for example a program that waits for an user to press a key and then read the R register, it might be at any value.
The most significant bit of R is not altered by the CPU refresh, so you can use it for any purpose, like store some important flag bit. But what does matter is that the whole 16-bit IR register contents are sent out to address bus. In theory you could toggle the MSB of the R register in a periodic timer interrupt to allow refreshing larger DRAMs with 256 rows.
Rtimes the horizontal sync in the ZX81. However, several graphic modes work differently and use it as lower address byte to address the graphics data. You need a patch that enables the RAM during/RFSH, too.