I've been reading on Makefiles, but I'm still clueless about how to go about writing the following commands into a Makefile.
gcc -std=c89 A.c -c gcc -std=c89 B.c -c gcc -std=c89 C.c -c gcc -std=c89 A.o B.o -o A gcc -std=c89 C.o B.o -o C A and C are dependent on B, but are separate programs.
This is what I came up with which doesnt work:
CC = gcc -std=c89 FILES = A.c B.c C.c OUT = out build: $(FILES) $(CC) -o $(OUT) $(Files) clean: rm -f *.o core This is a no gimmicks makefile, and what is before gcc and rm must be the 'tab' character, they are not spaces.
all: A C A.o: A.c gcc -std=c89 -c A.c B.o: B.c gcc -std=c89 -c B.c C.o: C.c gcc -std=c89 -c C.c A: A.o B.o gcc -std=c89 -o A A.o B.o C: C.o B.o gcc -std=c89 -o C C.o B.o clean: rm A C a.o b.o c.o core Try this:
X1 = A O1 = A.o B.o X2 = B O2 = C.o B.o DBGFLAGS = -g -O0 CFLAGS = -W -Wall $(DBGFLAGS) all: $(X1) $(X2) $(X1): $(O1) $(CC) $(LDFLAGS) -o $@ $(O1) $(LIBS) $(X2): $(O2) $(CC) $(LDFLAGS) -o $@ $(O2) $(LIBS) .PHONY: clean clean: rm -f $(X1) $(O1) $(X2) $(O2) *~ Change 8 spaces to one tab if the copy paste does not do it.
When you write a makefile, you generally start from the end, and work your way toward the beginning. You start from the final product, and give rules about how to produce that from the starting point(s).
In this case, you seem to have two final products: A and C.
all: A C If you don't specify a target on the command line, make will build the first target that it sees in the makefile. Therefore, you'd want this as the first target in the file, with the other targets below it. If you think of it as a tree, this is the root of the tree, and each item below is a branch of that tree.
It's also possible to define secondary targets that are not included below this root. Just for example, many (most?) makefiles include a target named clean that deletes all the intermediate files that would be created in the course of building. This will only be used when/if the user invokes make clean, not as part of just issuing make as a command.
Anyway, then you tell it about what each of those depends on, and how to create it from what it depends on:
A: A.o B.o $(CC) -o A A.o B.o C: B.o C.o $(CC) -o B B.o C.o Then (if necessary -- it's not here) you'd tell it about how each .o file depends on a .c file. Gmake, (like nearly ever make tool in existence) however, has builtin rules to tell it how to compile a C or C++ file to produce a matching object file. These will be about like your makefile contained something like this toward the top:
CC = gcc .c.o: $(CC) $(CFLAGS) -c $*.c That passes the current value of CFLAGS as flags to the compiler, so you want to set that to the flags you need -- in your case:
CFLAGS = -std=c89 You normally want to put that toward the top of the makefile, typically preceding any of the targets.
I should add that this doesn't even come close to covering everything you could do in a makefile. There are lots of shortcuts that come in really handy when you're dealing with a lot of files, but aren't really useful when you only have three source files.
C: C.o B.o)Assuming you use GNU make, you can mostly rely on built-in rules:
CFLAGS = -std=c89 LDFLAGS = -std=c89 A: A.o B.o C: C.o B.o This will perform the commands you listed. However, it doesn't care about cleaning or stuff like thet. You don't necessarily need that though - the make program will notice when things need to be recompiled/relinked and do so automatically.
%.o: %.c[ENTER][TAB]gcc -o $@ $< somewhere :-)