How to: multidimensional arrays in vhdl

Question

I'm trying to create a 5 dimensional array in VHDL but I'm unsure how I set and initialize the bits.

Here is what i have so far:

 type \1-line\ is array (4 - 1 downto 0) of unsigned (32 - 1 downto 0); type square is array (4 - 1 downto 0) of \1-line\; type cube is array (4 - 1 downto 0) of square; type hypercube is array (4 - 1 downto 0) of cube; type \5-cube\ is array (4 - 1 downto 0) of cube; signal mega_array : \5-cube\; begin process (clock, reset) begin if (reset == '1') then mega_array <= '0'; end if; end process; end behv;

vermaete · Accepted Answer · 2013-02-15 13:36:41Z

A way to do it is with '(others =>'0')'. This is a clean and safe way to set all bits of the vector at '0'. You have to do this for every layer of your array.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is port ( clock : in std_logic; reset : in std_logic); end entity test; architecture behv of test is type \1-line\ is array (4 - 1 downto 0) of unsigned (32 - 1 downto 0); type square is array (4 - 1 downto 0) of \1-line\; type cube is array (4 - 1 downto 0) of square; type \5-cube\ is array (4 - 1 downto 0) of cube; signal mega_array : \5-cube\; begin process (clock, reset) begin if (reset = '1') then -- note: not '==' mega_array <= (others => (others => (others => (others => (others => '0'))))); end if; end process; end architecture behv;

Note that although the \1-... naming is correct VHDL, I would not use it to avoid nasty tools issues. I'm not sure they will come, but avoiding them is better then solving them. I would use t_1line instead.

Martin Thompson · Accepted Answer · 2013-02-18 13:53:10Z

An aggregate is what you need:

(others => '0') sets all the bits in a vector to '0'

(others => (others => '0')) sets all the elements of an array of vectors to all bits '0'

(others => (others => (others => '0')))... etc. :)

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