In Verilog, what does a plus/minus sign after index do? [duplicate]

Question

For example, here:

a = b[16:0] + c[0+:WIDTH];

What does the + sign do? Let's say b was 16'h1234 and c was 16'ABCD.

I asked long time ago what was the meaning of +: Here is the link stackoverflow.com/questions/18067571/…. In that case B and C will be sum — DOS
– DOS, Commented Jan 7, 2014 at 22:13

Arash Fotouhi · Accepted Answer · 2014-01-07 21:48:53Z

4

reg1[a+:b] means start with "a" and increment index until "b" cells.

reg1[a-:b] means start with "a" and decrement index until "b" cells.

so

reg1[0+:8] is equivalent to reg1[0:7]

reg1[7-:8] is equivalent to reg1[7:0]

answered Jan 7, 2014 at 21:48

Arash Fotouhi

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1 Comment

Chiggs Over a year ago

Worth mentioning why this is important: It's not possible to perform slicing in the form reg1[i:i+8] as the compiler interprets this as a variable width slice. Therefore if trying to take a slice of a vector using a variable offset (e.g. in a loop) this notation must be used.

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