Address of interrupt handler in interrupt vector is +1 of actual address

Question

I cross compiled a program for cortex-m3. In start up code all interrupts are given in g_pfnVectors. When I disassemble, at address 0x0, I see "stack pointer value". Than at address 0x4 reset interrupt handler address is given. This keeps going with following system interrupt addresses.

Here is my question : Why in interrupt vector, addresses of interrupt handlers are +1 of the actual address. Address of ResetISR handler is 0x184 but in interrupt table it is 0x185. This is the case for all other interrupt handler addresses. What is the reason of this?

 00000000 <g_pfnVectors>: 0: 10008000 andne r8, r0, r0 4: 00000185 andeq r0, r0, r5, lsl #3 8: 00000215 andeq r0, r0, r5, lsl r2 c: 0000021d andeq r0, r0, sp, lsl r2 00000184 <ResetISR>: 184: b580 push {r7, lr} 186: b084 sub sp, #16 188: af00 add r7, sp, #0 ....... 00000214 <NMI_Handler>: 214: b480 push {r7} 216: af00 add r7, sp, #0 218: e7fe b.n 218 <NMI_Handler+0x4> 21a: bf00 nop ....... 0000021c <HardFault_Handler>: 21c: b480 push {r7} 21e: af00 add r7, sp, #0 220: e7fe b.n 220 <HardFault_Handler+0x4> .......

zenprogrammer · Accepted Answer · 2015-02-21 16:09:34Z

I found the answer in ARMv7-M Architecture Reference Manual, section Vector Table Definition(B1.5.3):

The Vector table must be naturally aligned to a power of two whose alignment value is greater than or equal to (Number of Exceptions supported x 4), with a minimum alignment of 128 bytes. On power-on or reset, the processor uses the entry at offset 0 as the initial value for SP_main, see The SP registers on page B1-572. All other entries must have bit[0] set to 1, because this bit defines the EPSR.T bit on exception entry. See Reset behavior on page B1-586 and Exception entry behavior on page B1-587 for more information. On exception entry, if bit[0] of the associated vector table entry is set to 0, execution of the first instruction causes an INVSTATE UsageFault, see The special-purpose program status registers, xPSR on page B1-572 and Fault behavior on page B1-608. If this happens on a reset, this escalates to a HardFault, because UsageFault is disabled on reset, see Priority escalation on page B1-585 for more information.

Long story short, bit 0 defines that the instruction is in thumb mode. Afaik.

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