How can I add a directory to the search path of GNU Make?

Question

I have a makefile that looks something like this:

include anotherFile.mk all: someStuff

The file anotherFile.mk is like this:

include yetAnotherFile.mk export SOME_VAR = 93

The problem is that anotherFile.mk and yetAnotherFile.mk are in a different directory from my Makefile. So my makefile can't just be changed to this:

include $(OTHER_PROJECT_PATH)/anotherFile.mk all: someStuff

The problem with this approach is that the include statement in anotherFile.mk will fail because it will be searching in the current directory.

A partial solution that I found is to pass the --include-dir=$OTHER_PROJECT_PATH flag to the invocation of make, but that's a bit user-unfriendly.

So my question is: Is there something I can put inside my makefile that will add to the directories that make searches for when executing an include? Something like MAKE_INCLUDE_DIRS += $(OTHER_PROJECT_PATH)

Come Raczy · Accepted Answer · 2017-01-19 01:03:21Z

Surprisingly there doesn't seem to be a good answer to that question. Forcing .INCLUDE_DIR doesn't help and there doesn't seem to be any way around invoking make with --include-dir=$OTHER_PROJECT_PATH.

It is however possible to put the appropriate recursive make invocation inside the makefile but, in order to get it to work for all reasonable cases it quickly becomes too complicated to be worth it. In summary it requires:

a top level condition to check if the OTHER_PROJECT_PATH is in .INCLUDE_DIR
the appropriate target with the recipe invoking make recursively
possibly additional targets if there are multiple command goals
the real make file enclosed in the else part of the conditional

You Makefile would look like this:

OTHER_PROJECT_PATH := other ifeq (,$(filter $(OTHER_PROJECT_PATH), $(.INCLUDE_DIRS))) # this is the mechanism to add the include dir in a recursive make $(or $(firstword $(MAKECMDGOALS)),all): $(MAKE) -I$(OTHER_PROJECT_PATH) $(MAKECMDGOALS) # add empty targets for additional goals if needed ifneq (,$(wordlist 2,$(words $(MAKECMDGOALS)),$(MAKECMDGOALS))) $(wordlist 2,$(words $(MAKECMDGOALS)),$(MAKECMDGOALS)): endif else # this is where the real makefile starts all more: echo $@: $< $^ include a.mak endif

user766308 · Accepted Answer · 2018-10-08 10:55:26Z

It still does not seem possible from a makefile, but if you have a script that sets up environment variables, you can use MAKEFLAGS (e.g. export MAKEFLAGS=I/your/path ordentlich on Linux, or SET on Windows)

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