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Question 1

I usually work with Xilinx FPGA boards. Based on the documentation I've reviewed and the research I've done, I try to avoid using a global reset signal in my designs as much as possible. However, let'...

Question 2

My register doesn't work properly. The output changes simultaneously with the input. There should be a one-cycle delay, but I am not seeing it from the simulation in Modelsim. Does anyone know why? ...

Question 3

I'm implementing a simple ARM7 in Verilog and am currently in the process of creating a simple data memory. I've come up with something like this: // very simple sdata implementation with 1mb~ memory ...

Question 4

I have a simple example for random stability in QuestaSim. module sv_rand_stability; class dummy; rand int data; endclass initial begin dummy d; $display("%...

Question 5

In SystemVerilog is the "property" construct: property <name> <body> endproperty This can then be instantiated as: assert property(<name>); In the language extension ...

Question 6

In UVM TLM1, there are three main interface types: port — the initiator of a transaction, export — a proxy that forwards port requests to an implementation, imp — the implementation, which contains ...

Question 7

Can someone help me with system verilog constraint for the below requirement.1) Fixed queue size of 10 and has four 6s in it at random position. I tried the below constraint to start with. class ...

Question 8

I'm writing an FPGA state machine in System Verilog to read bytes from a SPI port and parse them into commands to the FPGA. The "RXSPIBITS" state is used to read SPI bytes by multiple other ...

Question 9

I've been doing a finite state machine of an elevator using Verilog. The elevator contains four states: IDLE: When the elevator is stopped. ERROR: When the elevator's weight limit is exceeded. MOVING:...

Question 10

For context, please look at my attached diagram to see what I am trying to accomplish. Essentially, I want to swap inout wires using a contained hierarchy that will allow me to have more modular RTL ...

Question 11

I know a lot of people have asked about when to use assign inside always, but I'm wondering if you actually have to. Is it ok to have a module where you have assign statements, but they are not inside ...

Question 12

I’m working on an FPGA project and planning to use UVM (Universal Verification Methodology) for verification. I’m confused about the timing of when to apply UVM in the design flow. Should I develop my ...

Question 13

When I am doing some development with Verilog and Vivado, I wrote some Verilog code as follows: module min_rep_example_A(input clk, input rst_n, output reg[3:0] LED); always @(posedge clk or ...

Question 14

The instantiation module as below: module second_module( input [7:0] d, output reg [7:0] q ); initial q <= ~d; endmodule The top module as below: module top_module( input [7:0] ...

Question 15

Refer to this question,I write a similar case. module n; reg [1:0]a, b; initial begin a=1; a<=a+1; $strobe("strobe",a); $display("display",a); end endmodule The ...

Collectives™ on Stack Overflow

Proper way of resetting a FSM

Not seeing one-cycle delay for register in Modelsim

Why is my simple ARM7 data memory on Verilog failing tests?

Random stability with non-random object

Is conditional bracket pairing possible?

What's point of port to port type of connection in TLM? [closed]

System verilog constraint for queues with fixed number of 6s

In a System Verilog FSM can a repetitive State be converted to a Task?

How can I simulate a simple elevator FSM where it can detect overweight?

How to swap inout wires within a contained hierarchy (of which is synthesizable)?

Usage of assign: when to put it in an always or not [duplicate]

Should UVM testbench work with pre-synthesis or post-synthesis FPGA code? [closed]

In Vivado, what is "[Synth 8-7213] Expression condition using operand 'x' does not match with the corresponding edges used in event control" error?

Why does module instantiation affect output reg value in vivado? [duplicate]

`$strobe` and `$display` output different result for the same target

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