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Explore Stack Internal The usual way to create a 1:1 dependency in Makefiles is by using %, e.g.
%o:%cc Imagine I have 50 .cc files and I am interested in only 3 of them. I have constructed a list of their basenames:
CC_BASENAMES := Source15 Source32 Source41 How can I create a prerequisite for an .o file by iterating over the items in $(CC_BASENAMES). The effect should be equivalent to:
Source15.o: Source15.cc Source32.o: Source32.cc Source41.o: Source41.cc The usual way to create a 1:1 dependency in Makefiles is by using %, e.g.
%o:%cc Imagine I have 50 .cc files and I am interested in only 3 of them. I have constructed a list of their basenames:
CC_BASENAMES := Source15 Source32 Source41 How can I create a prerequisite for an .o file by iterating over the items in $(CC_BASENAMES)
The usual way to create a 1:1 dependency in Makefiles is by using %, e.g.
%o:%cc Imagine I have 50 .cc files and I am interested in only 3 of them. I have constructed a list of their basenames:
CC_BASENAMES := Source15 Source32 Source41 How can I create a prerequisite for an .o file by iterating over the items in $(CC_BASENAMES). The effect should be equivalent to:
Source15.o: Source15.cc Source32.o: Source32.cc Source41.o: Source41.cc The usual way to create a 1:1 dependency in Makefiles is by using %, e.g.
%o:%cc Imagine I have 50 .cc files and I am interested in only 3 of them. I have constructed a list of their basenames:
CC_BASENAMES := Source15 Source32 Source41 How can I create a prerequisite for an .o file by iterating over the items in $(CC_BASENAMES)