The usual way to create a 1:1 dependency in Makefiles is by using %, e.g.
%o:%cc Imagine I have 50 .cc files and I am interested in only 3 of them. I have constructed a list of their basenames:
CC_BASENAMES := Source15 Source32 Source41 How can I create a prerequisite for an .o file by iterating over the items in $(CC_BASENAMES). The effect should be equivalent to:
Source15.o: Source15.cc Source32.o: Source32.cc Source41.o: Source41.cc I'm not sure what you are asking, but there are several simple ways for manipulating strings.
For example, you can add the suffix .o to each of your basenames with OBJS = $(addsuffix .o,$(CC_BASENAMES)).
You can convert one suffix to another, for example $(OBJS:.o=.cc). So perhaps what you want is a Makefile such as
CC_BASENAMES := Source15 Source32 Source41 OBJS = $(addsuffix .o,$(CC_BASENAMES)) SRCS = $(OBJS:.o=.cc) fred.o: $(SRCS) cc $(SRCS) -o fred.o Or more usually you would define SRCS first and derive OBJS from it.
If you want a dependency rule to apply to just some targets, you can use targets: target-pattern: prereq-patterns ie
$(OBJS): %.o: %.cc See gnu make.
$(OBJS): $(@:.o=.cc) $(OBJS): %.o: %.cc Having a general build rule (like %o:%cc) doesn't mean that make will have to go though all 50 source files every time. What you need to do is specify a the output you want, and let make apply the rule to build it for you. E.g. you could run
$ make Source15.o Source32.o Source41.o on the command line, or create a specific target in your makefile
my_build: Source15.o Source32.o Source41.o and then ask make to build that target:
$ make my_build 
makeis a Unix tool.